ICE-DIP closing workshop
With the ICE-DIP project reaching its end date, we will be holding a two day event including a final joint work session with the Fellows, a supervisory board meeting, and a public presentation session.
The public session, open to any interested participants, will be held in the afternoon of September 14th in room 513-1-024.
Please consult the tentative agenda from the menu on the side and don't forget to register if you wish to take part.
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09:00
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12:30
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12:30
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14:00
Self Service at the Restaurant 2 (just opposite the street from the Computer Center building 513): Lunch Restaurant 2
Restaurant 2
CERN
Please bring some cash CHF.
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14:00
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16:30
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16:30
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18:00
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19:00
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22:00
Informal dinner: Dinner at Restaurant Rita et Albert
Transport will be organised with private cars from CERN to the restaurant at 19h.
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09:00
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12:30
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09:00
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12:30
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11:00
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14:00
Supervisory board meeting: Supervisory board meeting with lunch 513/1-024
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11:00
Welcome and validation of agenda 5m
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11:05
Statements from ESRs 30m
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11:35
Review of actions and approval of minutes 10m
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11:45
Project status and plans for the 4th year 15m
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12:00
ICE-DIP survey summary and discussion on findings 20m
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12:20
Public session agenda 5m
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12:25
AOB 5m
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11:00
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12:30
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14:00
Self Service at the Restaurant 2 (just opposite the street from the Computer Center building 513): Lunch Restaurant 2
Restaurant 2
CERN
Please bring some cash CHF.
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14:00
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17:30
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14:00
Introduction to ICE-DIP and this session 10mSpeaker: Bob Jones (CERN)
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14:10
ICE-DIP - key technical points 10mSpeaker: Andrzej Nowak
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14:20
Software Switching for Data Acquisition 20m
In this talk we discuss the feasibility of replacing telecom-class routers with a topology of commodity servers acting as software switches in data acquisition. We extend the popular software switch, Open vSwitch, with a dedicated, throughput-oriented buffering mechanism. We compare the performance under heavy many-to-one congestion to typical Ethernet switches and evaluate the scalability when building larger topologies, exploiting the integration with software-defined networking technologies.
Please note that David Malone will speak on behalf of Grzegorz Jereczek.
Speakers: Mr David Malone, Grzegorz Jereczek (CERN) -
14:40
Radiation-hard silicon photonics for high energy physics and beyond 20m
Silicon photonics (SiPh) is currently being investigated as a promising technology for future radiation hard optical links. The possibility of integrating SiPh devices with electronics and/or silicon particle sensors as well as an expected very high resistance against radiation damage make this technology particularly interesting for potential use close to the interaction points in future in high energy physics experiments and other radiation-sensitive applications. The presentation will summarize the outcomes of the research on radiation hard SiPh conducted within the ICE-DIP projected.
Speaker: Marcel Zeiler (CERN) -
15:00
FPGAs for next gen DAQ and Computing systems at CERN 20m
The need for FPGAs in DAQ is a given, but newer systems needed to be designed to meet the substantial increase in data rate and the challenges that it brings. FPGAs are also power efficient computing devices. So the work also looks at accelerating HEP algorithms and integration of FPGAs with CPUs taking advantage of programming models like OpenCL. Other explorations involved using OpenCL to model a DAQ system.
Speaker: Srikanth Sridharan (CERN) -
15:20
Group Photo 10m
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15:30
Break 30m
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16:00
Data transfer on manycore processors for high throughput applications 20m
In this talk I will present my efforts to implement a data transfer mechanism for the Intel Xeon Phi Coprocessor and its integration in the ZeroMQ message queue library. The latter is used extensively at CERN to support online and offline processing. Finally I will share my experience in the CERN openlab ICE-DIP project.
Speaker: Aram Santogidis (CERN) -
16:20
The consequences of poor vectorization 20m
This talk briefly discusses the vectorization problem and how it impacts scientific and engineering systems. A simple cost model of designing such system in context of different phases of software lifetime is considered. Finally a concept for scalable solution is presented.
Speaker: Przemyslaw Karpinski (CERN) - 16:40
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17:00
Closing statements - Intel 10mSpeaker: Joe Butler (Intel Labs Europe)
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14:00
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17:30
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18:30
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09:00
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12:30