CRU Weekly Meeting

Wednesday 28 Sept 2016, 10:30 → 12:30 Europe/Zurich

CERN

CRU Weekly meeting (28 Sept 2016)

Present: Erno, Jubin, Sanjoy, pippo, mazsi, Torsten

Secretary: Erno(8), PiPPo(7), Shuaib(1), mazsi(5)

Actions:

• all: keep preparing answers to EDR questions.
• shuaib will report back when we can start accessing remotely the Arria10 card they have received in kolkata.

Report on Actions:

• date of EDR follow up: not set yet, will be aligned with prototype FW release.
• access to Arria10 card in kolkata: still not accessible, datacenter firewall prevents it. need to work on that
  (shuaib not present, report from jubin).
• XCVR clocking presentation was checked: generic pre Arria10, nothing about fPLL aging.

1. 10G PON

• small timing improvement.
• no update from altera on 2UI error.

2. GBT

• component is now based on the tx_clock_bonding (x6/xN), this is the planned solution for the prototype fw.
• this clocking mode supports (5 bank * 6 link / bank =) 30 links.
• feedback compensation: also enabled, phase to be checked in hw.
• based on GBT 4.0.0, not on the latest GBT (4.0.1) release. no issue known that would force us to upgrade.
• timing issues when crossing from hard XCVR block into FPGA fabric: 0 levels of logic, but long clock path.
• todo: adapt simulation to changes.
• todo: wide bus mode support dynamic switching - but for prototype fw: we can instantiate 2 blocks (one in wide mode, other not, and mux before/after them).

3. DCS

• No update.

4. PCIe

• work on FIFO like interface for data input.
• single clock FIFO in separate design: works (solved error: 1 word data corruption on transfer boundary).
• dual clock FIFO in integrated design: not yet (data doesn't move from FIFO to PC memory).

5. Integration

• GBT -> datapath -> PCIe connected, not working yet, pippo + sanjoy working on it.
• versioninfo registers are there.

AOB

• Torsten (in contact with pippo): we should have hw support for bit error testing on GBT links.
  GBT test patterns will probably do (no other solution for simplex links in TPC [GBTX @ FEC -> CRU])
  we already have some version, to be checked if it's enough / compatible with latest GBT ASIC.

Vacations

• PiPPo at CERN on conference 10-14 october, on leave until 7 november (but can work remotely).
• mazsi: oct 13-18: at wigner / budapest.