A radiation-tolerant CDR/PLL macro-block has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and reference-less Clock and Data Recovery (CDR), showing deterministic phase and less than 10 ps rms total jitter between 10 kHz and 10 MHz integration bandwidth. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs for GBT-FPGA applications or providing 40, 80, 160 and 320 MHz clocks for TTC and e-link applications. The CDR operates with 40, 80, 160 or 320 Mbit/s data rates while always generating clocks at 40, 80, 160 and 320 MHz, regardless of the data rate. All outputs are phase programmable with a resolution of 195 ps or 260 ps depending on the selected mode. The eCDRPLL macroblock has been designed using radiation-tolerant techniques in an 130 nm CMOS technology and has been instantiated in the Velopix ASIC. The macroblock topology, the adopted design flow and experimental results will be presented.
