The talk will explore the challenges faced in the verifi?cation of the ALPIDE chip and discuss the solutions adopted. The chip and its use cases will briefly be presented. A succinct overview of the UVM-based environment supporting the functional verifi?cation of the chip will then be given. Solutions to practical problems will then be described in the hope of aiding future developments. Firstly, techniques used to optimise the use of computing resources and accelerate simulation will be discussed. These include incremental snapshot elaboration, dynamic DUT con?figuration and behavioural matrix modeling. Secondly, the SEU protection design technique adopted and the veri?fication measures taken to ensure none of the triple module redundancy (TMR) circuitry is simplifi?ed will be discussed. Finally, some examples will be provided to illustrate the bene?fits of incorporating assertion based veri?fication (ABV) within the environment. Properties will also be used to present a worked Formal Veri?fication example and show the benefi?ts of using both Simulation and Formal in parallel.