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    Developer's meeting

    → Europe/Zurich
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    present: Giovanna, Enrico, Roland, Eric, Lynn, Rene, Milo, Frank

    Roland, Enrico:

    • can now use the official Felix s/w suite (thanks to Andrea et al.)
    • hardware loop-back not yet operational
    • good progress on software (BoardReader) side:
      • NetIO publisher using Milo's frame generator (providing a data source)
      • investigating several options for circular buffer (default: single-producer-single-consumer implementations; but also want to look at a multiple-producers-multiple-consumers implementation)
      • HWInterface (as artDAQ type): subscribes to 2 NetIO links (on a single socket) and features a single circular buffer
      • meant to be flexible; NetIO configuration added to FHiCL files (BoardReader parameter set)
    • discussion:
      • Eric: are you waiting for Andrea to provide new s/w, f/w? Roland: yes, some issues with timing, also framework needs to be updated
        •  need to use TTCfx for improved clocking (jitter cleaning)? Giovanna: should see if we can do without this
      • Giovanna: can you respond to readout requests at this point (this would be desirable for the upcoming Milestone week)? Enrico: not yet

    Rene:

    • starting point for WIB data emulation: Felix firmware itself, but stripped GBT wrapper and TTCfmc code off
      • idea: allow for internal data generation (a simple counter) or receive data (through DMA transfer) from PC application (not yet attempted to test this)
    • planning for 3 data paths:
      •   1: internal generation, loop-back, read data back using internal logic analyzer core
      •   2: internal generation, loop-back, DMA transfer to Felix PC application
      •   3: internal generation or from PC application, read back using another VC709 card
    • present status: still stuck at step 1, data are not coming out of the transceiver correctly
    • next steps: also want to add "proper" timestamps and allow for multiple link IDs
    • discussion:
      • Kevin: what fibers -- SFP or CXP? Rene: the fiber shown in the figures is the wrong one
      • Frank: what clock issue? Rene: presumably use of 40.08 MHz instead of 40 MHz precisely, likely this will be seen as a "dirty" clock. Enrico: could be the same issue as seen from the CERN side
      • Milo: what PC application? Rene: don't know yet. Giovanna: it would make most sense to use the frame generator, and add a DMA output rather than NetIO

    AOB:

    • next meeting: a priori in 2 weeks from now (even if it is a Milestone week it should be possible to find time for that)
    • Frank will collect material for report in Monday's DAQ meeting (in preparation for Milestone week)

     

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