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EP-ESE Electronics Seminars
Analog/Mixed-Signal Design in finFET Technologies
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Europe/Zurich
13/2-005 (CERN)
Description
Continued consumer demand for mobile ICs has propelled CMOS scaling to arrive at the finFET with foundry offerings starting at 16/14 nm. The compact 3-D structure of the finFET offers superior short-channel control that achieves digital power reduction and adequate device performance. As SoC technology remains dictated by logic and SRAM scaling needs, designers of analog/mixed signal subsystems must adapt to new design constraints. We attempt to summarize the challenges and considerations faced when porting analog/mixed-signal designs to finFET. At 16/14 nm, designers must also cope with many accumulated implications of earlier scaling innovations leading to the finFET.
Alvin Loke received a B.A.Sc. in engineering physics from the University of British Columbia, and M.S. and Ph.D. in electrical engineering from Stanford. He worked on CMOS process integration for several years at HP Labs and on assignment at Chartered Semiconductor. Since 2001, he has been designing circuits for a variety of wireline links and addressing next-generation CMOS analog/mixed-signal concerns at Agilent and Advanced Micro Devices in Fort Collins, CO, and most recently at Qualcomm in San Diego, CA. He has authored several dozen publications and holds 19 US patents. Alvin has served as Technical Program Committee member of CICC, IEEE Chapter Chair, Guest Editor of the IEEE Journal of Solid-State Circuits, and IEEE Distinguished Lecturer.
