CERN Computing Seminar

Accessing Intel FPGAs for Acceleration

by Karl Qi (Intel Corp.)

31/3-004 - IT Amphitheatre (CERN)

31/3-004 - IT Amphitheatre


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In this presentation, we will discuss the latest tools and products from Intel that enables FPGAs to be deployed as Accelerators. We will first talk about the Acceleration Stack for Intel Xeon CPU with FPGAs which makes it easy to create, verify, and execute functions on the Intel Programmable Acceleration Card in a Data Center. We will then talk about the OpenCL flow which allows parallel software developers to create FPGA systems and deploy them using the OpenCL standard. Next, we will talk about the Intel High-Level Synthesis compiler which can convert C++ code into custom RTL code optimized for Intel FPGAs. Lastly, we will focus on the task of running Machine Learning inference on the FPGA leveraging some of the tools we discussed.

About the speaker

Karl Qi is Sr. Staff Applications Engineer, Technical Training. He has been with the Customer Training department at Altera/Intel for 8 years. Most recently, he is responsible for all training content relating to High-Level Design tools, including the OpenCL SDK, HLS Compiler, and DSP Builder as well as Machine Learning applications. Prior to joining Altera/Intel, he was with Lockheed Martin Space Systems. Overall he has 15 years experience with FPGAs.

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