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Developer's meeting
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Europe/Zurich
Present: Enrico, Roland, Junbin, Shanshan, Milo, Frank
EHN1 (Enrico, Roland, Milo):
- h/w: server shipped by Jos to CERN, can be used to house a VC709 card; should arrive on Friday
- f/w:
- debug session last week, problem starting fdaq even with 2 DMA instances; reproducible (also by Frans, Jos, Henk):
- soft_reset independently causes issues, being looked into by Frans
- DMA pointer issue. Frans: related to DMA, invalid read pointer (corrupted)
- f/w issue: from ~ 7 links, missing words after ~ 200 s (causing fdaq crash), worse if more links
- probably words lost in f/w FIFOs; now trying a build with deeper FIFOs
- but not seen w/ superchunks when using start-up sequence suggested by Frans
- still issues (in simulation) when using anything else than 2 idles (i.e., for actual WIB data there is an issue): unexpected chunk sizes
- proposal (for now) is to focus on the version with superchunks (and not prioritise changing FIFO depths)
- now have help also from René
- debug session last week, problem starting fdaq even with 2 DMA instances; reproducible (also by Frans, Jos, Henk):
- s/w:
- propose to work only w/ felixcore, not with fdaq (especially given the time pressure; there are too many differences between the two)
- Infiniband: now working in BR with NetIO, but still some issues whenever the link dies
- expect that server shipped by Jos will help with CPU load
- now have help from Thijs (summer student of Roland's) working on analytics and also in contact with Milo about compression (re-ordering code)
- would be good to see if he can also study the use of AVX (or rather AVX512) instructions
- compression:
- now studying the MicroBooNE data
- discussion on what to do with CRC words
- (Enrico:) frame checksum already removed by FELIX (and replaced with a single bit to flag errors)
- in the superchunks implementation this bit is not retained though. We should do so, if at all possible
- and the COLDATA checksums should be dealt with in the same way (but in the BR code)
- schedule: expect to have to start reading out on Sunday
WIB (Junbin):
- now focusing on BNL f/w
- fixed several bugs in f/w and in configuration
- also found timing constraint issue due to (nested) logic in CRC code; replaced with pipelined version
- reported this to the FELIX team (FLXUSERS-173) but for Xilinx apparently this is not an issue, while for Altera it is
- would be good to port f/w fixes also to system used at CERN
- still need to integrate timing system in f/w
AOB:
- comments on Enrico's slides for CHEP welcome
- next meeting: no firm decision, FF will be on vacation in the next weeks, propose that Giovanna arrange for this if needed
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