System-on-Chip Workshop - CERN

Session

Overview and Use Cases

12 Jun 2019, 13:30

40/S2-C01 - Salle Marie Sklodowska-Curie (CERN)

Conveners

Overview and Use Cases

• Ralf Spiwoks (CERN)
• Revital Kopeliansky (Indiana University (US))

6. Evolution of CMS online system and role of SoC

Frans Meijers (CERN)

12/06/2019, 13:30

7. ATLAS SoC - Review

Revital Kopeliansky (Indiana University (US))

12/06/2019, 13:55

8. ATLAS MUCTPI and System on Chip

Ralf Spiwoks (CERN)

12/06/2019, 14:20

The Muon to Central Trigger Processor Interface (MUCTPI) is a key element of the first level, hardware trigger of the ATLAS experiment. It is being upgraded for the next run of the Large Hadron Collider (LHC) at CERN. The new MUCTPI is implemented as a single ATCA blade with high-end processing FPGAs for the low-latency, parallel trigger processing. A Xilinx Zynq System-on-Chip (SoC)...

9. Fault Resilient Design for 28nm ZYNQ SoC based Radiation Protection Monitoring System Fulfilling Safety Integrity Level 2

Hamza Boukabache (CERN)

12/06/2019, 14:40

CERN Radiation Protection is developing a state-of-the-art radiation monitor, CROME (CERN RadiatiOn Monitoring Electronics), measuring dose rates from 50nSv/h over a range of 9 decades without auto-scaling. Converted into electrical current, the frontend electronics accurately (+-1%) measures from 1fA to 1uA.

CROME’s main purpose is to measure radiation across CERN sites to protect persons...

10. SoC technology for embedded control and interlocking within fast pulsed systems

Pieter Van Trappen (CERN)

12/06/2019, 15:30

The control of CERN’s beam-transfer kicker magnet high-voltage pulse generators requires often the use of digital control in FPGAs to allow tight timing control (jitter better than one ns) and fast protection of the high-voltage thyratron and semiconductor switches. A FPGA is a perfect candidate for the digital logic, it is however limited in integration possibilities with the actual and...

11. The CMS APx Platform using SoC Devices

Thomas Andrew Gorski (University of Wisconsin Madison (US))

12/06/2019, 15:50

The APx platform encompasses multiple ATCA blade types, supporting CMS Phase 2 detector back end FPGA-based processing. Central to the APx architecture are two custom-designed ZYNQ mezzanines. The ZYNQ-IPMC is a DIMM form-factor, enhanced IPM controller for ATCA, with primary responsibility for sensor and power control. The Embedded Linux Mezzanine (ELM), has primary responsibility for...

12. CMS R&D for Phase-2 Tracker Back-end Electronics

Luis Ardila (KIT-IPE)

12/06/2019, 16:15

The Phase 2 CMS tracker back-end processing system is composed by two types of "Detector, Trigger and Control" (DTC) boards interfacing the inner and outer tracker, and by the "Track Finding Processor" (TFP) board performing level-1 track reconstruction from the outer tracker data. Several groups are building hardware to prove key and novel technologies needed in the back-end processing...

19. Speaker 7

17. Tutorial 4

2. Xilinx