System-on-Chip Workshop - CERN

Session

Manufacturer Presentations

12 Jun 2019, 09:00

40/S2-C01 - Salle Marie Sklodowska-Curie (CERN)

Conveners

Manufacturer Presentations

• Revital Kopeliansky (Indiana University (US))
• Ralf Spiwoks (CERN)

1. Workshop Introduction & Motivation

Ralf Spiwoks (CERN)

12/06/2019, 09:00

3. Xilinx - Roadmap to 7nm Versal Family

Kester Aernoudt (Xilinx)

12/06/2019, 09:10

The Zynq UltraScale+™ MPSoC (Multi-Processing System on Chip) is the second generation of SoC following the 28nm Zynq- 7000 All Programmable SoC. Xilinx has developed the architecture based on the most advanced TSMC 16nm FinFET process technology for high performance and power efficiency.
The Zynq UltraScale+ MPSoC boasts over 6000 interconnects linking the processing system and programmable...

4. Intel/Altera - SoC R&D plans

Kris Chaplin (Intel)

12/06/2019, 10:40

This presentation will discuss the families of Intel SoC FPGA devices from 28nm Cyclone V SoC through to the newly-announced 10nm Agilex SoCs. Starting off with a discussion of the benefits of integrating processor and FPGA onto a single die, detail will be given as to use cases for their application and technical differences and evolutions between the family members and their evolution over...