Intel HLS Workshop

4/3-006 - TH Conference Room (CERN)

4/3-006 - TH Conference Room


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    • 9:00 AM 10:30 AM
      Acceleration Stack workshop 1h 30m

      The Intel® Acceleration Stack for Intel Xeon® CPU with FPGAs is a robust collection of software, firmware, and tools designed and distributed by Intel to make it easier to develop and deploy Intel FPGAs for workload optimization in the data center. The Intel® Acceleration Stack for Intel Xeon® CPU with FPGAs provides multiple benefits to design engineers, such as saving time, enabling code-reuse, and enabling the first common developer interface.

      • Introduction and acceleration stack overview
      • Getting Started with the Acceleration Stack
      • Developing a SW host application
      - LAB 1
      • Introduction to Accelerator Functional Unit (AFU)
      • Creating an Accelerator Functional Unit (AFU)
      • Co-simulation using AFU Simulation Environment (ASE)
      • Compiling the Accelerator Function Unit into an Accelerator Function (AF)
      • Debugging an Accelerator Function
      - LAB 2

    • 10:30 AM 11:00 AM
      Coffee break 30m
    • 11:00 AM 1:00 PM
      HLS development flow - part 1 2h

      The Intel® HLS Compiler is a high-level synthesis (HLS) tool that takes in untimed C++ as input and generates production-quality register transfer level (RTL) code that is optimized for Intel FPGAs. This tool accelerates verification time over RTL by raising the abstraction level for FPGA hardware design. Models developed in C++ are typically verified orders of magnitude faster than RTL.

      • Introduction to high-level synthesis with the Intel® HLS Compiler
      - Lab on HLS Flow

      Speaker: Bill Jenkins (Intel)
    • 1:00 PM 2:30 PM
      LUNCH 1h 30m
    • 2:30 PM 4:30 PM
      HLS development flow – part 2 2h


      • Loop Parallelization
      - Lab on Loop Optimizations
      • Using Appropriate Data Types (Optional based on time)