15–20 May 2022
University of Sussex
Europe/London timezone

Design and Power management issues in the CALICE SiW ECAL base elements

Not scheduled
20m
University of Sussex

University of Sussex

Falmer Campus, Brighton, Sussex, BN1 9QH, United Kingdom

Speaker

Roman Poeschl (Université Paris-Saclay (FR))

Description

Performant electromagnetic calorimeters suited for a Particle Flow approach rely on their granularity and compactness to unravel the contributions of nearby showers. For practical reasons, their readout electronics must be close to the sensors, hence present a very low power dissipation, in a scalable geometry allowing for long (~1.5–1.8 m) detector cassettes serviced from a single end. To do so, near linear colliders, detector electronics can be pulsed. The aforementionned requirements apply to the very front-end ASICs but equally to the supporting PCB’s. The technological prototype of the CALICE SiW ECAL is testing solutions for an ILC-like environnement, based on 18×18 cm² front-end boards, holding 16 SKIROC2 ASICs and 4 matrices of silicon diodes. Five versions of these boards, using either packaged or naked chips, have been integrated, and recently tested in beam, in a stack of 15 single-board layers, and in long layer of 8 boards. Lessons learned from these tests will be discussed in this contribution, as well as the new, improved, design, including on-board power regulations.

Author

Roman Poeschl (Université Paris-Saclay (FR))

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