Oct 19 – 23, 2020
Europe/Zurich timezone

Accelerated pixel detector tracklet finding with Graph Neural Networks on FPGAs

Oct 21, 2020, 2:00 PM
20m
Regular talk 1 ML for data reduction : Application of Machine Learning to data reduction, reconstruction, building/tagging of intermediate object Workshop

Speaker

Savannah Jennifer Thais (Princeton University (US))

Description

Track finding is a critical and computationally expensive step of object reconstruction for the LHC detectors. The current method of track reconstruction is a physics-inspired Kalman Filter guided combinatorial search. This procedure is highly accurate but is sequential and thus scales poorly with increased luminosity like that planned for the HL-LHC. It is therefore necessary to consider new methods for representing and reconstructing tracks.

This work makes use of Graph Neural Networks (GNNs) to explore possible improvements to track finding efficiency in the HL-LHC environment. A graph is constructed from each event by mapping hits in the pixel detector to graph nodes and constructing connecting edges using a physics-driven pre-processing. An edge-classification GNN is then used to assign physics-based probabilities to the connections. Finally, a post-processing algorithm is applied to iterate through the GNN labeled edges and form final track candidates.

We focus on a specific HL-LHC use case: tracklet finding in the innermost pixel detector using the expected Phase 2 geometry. Both ATLAS and CMS utilize inside-out track reconstruction algorithms that are seeded from the pixel detector making this a critical computing problem for HL-LHC development. This study will provide insight into the impact these novel algorithms can have on compute-intensive and physics-critical reconstruction.

The GNN-based tracking can be further accelerated by implementing the inference network directly on FPGAs. This would improve the computational throughput of a critical reconstruction step and could allow the GNN algorithm to be used in the High-Level Trigger system.

This talk will present and compare a variety of graph construction methods, GNN architectures (GCNs, edge convolutions, and Interaction Networks), post-processing track finding (Union Find and DBScan), and data augmentations that have been explored to understand the balance between tracking accuracy and algorithmic processing efficiency. We will also present initial studies on implementing these GNNs and related algorithms on FPGAs.

Primary authors

Savannah Jennifer Thais (Princeton University (US)) Lindsey Gray (Fermi National Accelerator Lab. (US)) Markus Julian Atkinson (Univ. Illinois at Urbana Champaign (US)) Gage DeZoort (Princeton University (US)) Isobel Ojalvo (Princeton University (US)) Mark Neubauer (Univ. Illinois at Urbana Champaign (US)) Javier Mauricio Duarte (Univ. of California San Diego (US)) Vesal Razavimaleki Aneesh Heintz (Cornell University)

Presentation materials