Single Event Multiple Transient Analysis of Digital Circuits using Satisfiability Modulo Theories

8 Dec 2022, 14:20
50m
503/1-001 - Council Chamber (CERN)

503/1-001 - Council Chamber

CERN

162
Show room on map

Speaker

Otmane Ait Mohamed (Concordia University)

Description

In this talk, we will be discussing the practical use of formal based techniques, such as SAT, SMT and probabilistic model checker to analyze SEEs at logical and higher abstraction levels. Through examples, we will illustrate each approach and its benefits.

Presentation materials