Speaker
Raoul Velazco
(TIMA)
Description
Perturbations provoked by Single Event Upsets (SEUs) increase with the reduction of transistor's features. In this talk will be presented a strategy allowing to estimate SEU error-rates based on a limited radiation ground testing and fault injection results. A flexible and versatile test platform, well suited to implement such a strategy will be described. Experimental results obtained for different processors illustrate the accuracy of error rate predictions.
