Speakers
Description
The Electron-ion collider in China (EicC) is a future high-energy nuclear physics project. It will be constructed based on an upgraded heavy-ion accelerator, High-Intensity heavy-ion Accelerator Facility (HIAF), which is currently under construction, together with a new electron ring. Due to its high spatial resolution, low material budget, and fast readout speed, the Monolithic Active Pixel Sensor (MAPS) has been chosen for the vertex detectors of the EicC. Charge deposited by the Minimum Ionizing Particles (MIPs) that pass through the MAPS is collected by the charge sensing node, formed by an n-well/p-substrate junction. Hence, the CMOS process is vital for developing MAPS.
The Nupix-A2, a MAPS with a pixel pitch of ~30µm, is designed for the EicC. The cost and detecting efficiency are the key concerns for CMOS process selection. Two 130nm CMOS processes have been proposed as candidates for this Nupix-A2. The first one is a commercial standard twin-well low resistivity (<50Ω·cm-3) process, and the other one is a quadruple-well high resistivity (>1kΩ·cm-3) process. A 3-dimensional TCAD model has been established to evaluate these two processes' feasibility for Nupix-A2. This paper will discuss the simulation and analysis of the effects of the MIPs on the Nupix-A2, which includes the study of the thickness of the depletion layer, charge collection efficiency, and charge collection time with different bias voltages and MIPs hitting locations.
