Speaker
Summary
The upgrade plans on the ATLAS hadronic calorimeter (TileCal) include the full readout of all data to the counting room. In order to study functional requirements of the future upgraded TileCal readout system we have assembled a minimal TDAQ slice. The aim is to implement a tentative readout chain for TileCal, starting with a newly developed 3-in-1 FE-board from University of Chicago and ending with the storage of triggered data on a PC. Later we will use PMT pulses, amplified and shaped by the 3-in-1 board, as a data source. However, for simplicity we start by using well defined calibration pulses also generated by the 3-in-1 board. The pulses are sampled by a 12 bit ADC, which is connected to an ML605 evaluation board from XILINX. These boards emulate the new on-detector electronics. The ML605 communicates via two 5Gb/s optical links with a Virtex-6 FPGA development board from HighTech Global which emulates the off-detector electronics. The off-detector board is situated in a PC and uses PCIe for readout and control. PCIe is a common ATCA protocol and ATCA will probably be the crate technology of choice. Using this setup we are able to test different parts, alone and together, which are critical for the further upgrade development. This would include new components, new firmware, clock distribution and recovery using the GBT-FPGA protocol as well as the development of software for monitoring and control.
The critical functionality of the setup has been developed and tested separately. Charge injection pulses produced in the 3-in-1 card have been controlled and recorded by the ML605 FPGA. The GBT FPGA-FPGA link has been thoroughly tested. Finally we have also tested the PCIe transfer. After verifying the functionality of the full chain the aim is to successively replace parts in the testbed to increase the realism of the model. The next step will be to replace the ML605 with purpose developed circuit boards which may be considered as an early prototype.
