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SoC Organising Committee02/10/2023, 09:30
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Edouard Lepape (NanoXplore)02/10/2023, 09:40
NanoXplore is introducing a state-of-the-art radiation hardened SoC FPGA portfolio offering unprecedented reliability performance. The NG-ULTRA is the first fully radiation hardened SoC FPGA in 28nm FD-SOI based on a quad core ARM R52 processor. The NG-ULTRA and ULTRA300 are the perfect candidates to address the most challenging Hi-Rel application requirements with a simple and cost-effective...
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All vendors02/10/2023, 10:40
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Gregory Donzel (Avnet SIlica)02/10/2023, 13:30
XILINX became AMD about 2 years ago: the FPGA/SoC strategy has been strengthened and innovation goes on… Following 16nm technology and the Zynq US+ SoC, Versal Adaptive SoCs now complete the AMD offering with 7nm products. This presentation will go through the different Versal Adaptive SoC series with a clear status of their availability and an overview of the roadmap. In addition to SoCs, AMD...
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Gregory Donzel (Avnet Silica)02/10/2023, 14:30
With many acquisitions over the last 10 years, MICROCHIP has become a broadline semiconductor manufacturer. After acquiring MICROSEMI (that acquired ACTEL before), MICROCHIP added FPGAs and SoCs in its portfolio. MICROCHIP has always had a good reputation for the very long longevity of their products. In addition to this key asset, they bring other significant differentiators to the FPGA/SoC...
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Oliver Bruendler (Enclustra)02/10/2023, 15:50
Explore efficient FPGA SoC-based signal processing for Giga sample per second (GS/s) rates. Tackle traditional DSP design challenges, address sample rates surpassing clock frequencies through Parallel DSP, and emphasize bit-true design. Discover how Enclustra's fixed-point & bit-true Python & HDL libraries offer a streamlined, step-by-step design and co-simulation process, enabling high-speed,...
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Samir Jokar (Enclustra)02/10/2023, 16:20
This presentation presents a comprehensive overview of the Enclustra FPGA solutions ecosystem. We offer a full spectrum of Hardware solutions, from FPGA SoC modules and baseboards to development kits. On the other hand, we provide top-notch engineering services, ensuring seamless integration and customization. Finally, we pride ourselves on responsive customer support, assisting at every stage...
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Vadim Yunitski (Trenz Electronic)02/10/2023, 16:50
For many years, Trenz has been at the forefront of specializing in the development and production of diverse modular systems, offering a wide array of benefits across numerous application domains. Our products accelerates end-device development, streamlines prototyping, and diminishes the skill demands placed on your hardware design team. One of the most important advantages is the reduction...
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Dirk van den Heuvel (Topic)03/10/2023, 09:30
Over the years, the complexity of circuits around system-on-chips has been growing rapidly. Apart from that, the core functionality offered by the SOCs also grew exponentially. When you look at typical applications using SOCs, you see a balance between processing performance, communication bandwidth and storage capabilities. The use of system-on-modules is helping to reduce the design-in...
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All vendors03/10/2023, 10:30
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Marco Hoefle (Avnet SIlica)03/10/2023, 13:30
Image processing algorithms as well as many other algorithms can often not be deployed on classical SoCs with the required performance.
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A Sobel filter, applied to a 4k video stream, might bring embedded processors as well as normal desktop PCs to its limit.
With Vitis HLS algorithms written in C/C++ can be deployed on FPGA logic.
In this presentation a Sobel filter will be running in the... -
Ralf Spiwoks (CERN)03/10/2023, 14:30
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Gabriela Cabrera Castellano (CERN)03/10/2023, 14:50
The Beam Instrumentation group at CERN utilizes Timepix3 hybrid pixel detectors for various applications, such as measuring the transverse beam profile through the Beam Gas Ionization profile monitor (BGI) and detecting beam losses with the Beam Loss Monitor (BLM). To effectively handle events and to control and monitor these detectors, the Beam Instrumentation PiXeL (BIPXL) MPSoC Readout...
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Irene Degl'Innocenti (CERN), Andrea Boccardi (CERN), Elif Balci (CERN), Manuel Gonzalez Berges (CERN), Michal Krupa (CERN), Stephen Jackson (CERN)03/10/2023, 15:40
The future HL-LHC Beam Position Monitor (BPM) data acquisition system to be installed near the ATLAS and CMS experiments is an application with demanding digitization and signal processing requirements. The architecture under study is based on an RF System-on-Chip from Xilinx, which allows fast RF conversion and high-performance digital processing to be integrated in a single chip for multiple...
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Aleksei Greshilov (Rice University (US)), Alexander Madorsky (University of Florida (US)), Michail Bachtis (University of California Los Angeles (US))03/10/2023, 16:10
The presentation will discuss the latest updates of the X2O platform for the upcoming Phase-2 upgrade. The X2O platform is a modular system in ATCA standard that includes hardware, firmware and software solutions. Main updates of the X2O platform include:
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Migration to the KRIA SoM (Ultrascale+ family) as a system controller and IPMC host within the power module (rev.3). Adaptations for VU13P... -
Risto Pejasinovic (University of Novi Sad (RS))03/10/2023, 16:40
SoCMake is a build system for hardware designs. SoCMake covers all the segments of SoC design, eliminating the need for additional build systems within a project.
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The Focus of SoCMake is on packaging hardware IP blocks in self-contained repositories that can easily be fetched and versioned with the CPM package manager. SoCMake uses CMake interface libraries to represent hardware IP blocks,... -
Clyde Laforge (CERN)03/10/2023, 17:10
SoC projects face the challenges of maintaining a manageable and comprehensible codebase that spans a wide range of technologies. Efficient use of resources is of paramount importance in order to enable small teams to lead such projects to success.
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This presentation will discuss the modern approach used in the CROME project not only to face these challenges, but also to ensure that improved... -
Dr Sebastian Kalcher (Nvidia)04/10/2023, 13:30
In the dynamic landscape of modern data centers, efficiency, performance, and security are paramount. NVIDIA Data Processing Units (DPUs) have emerged as game-changers in addressing these critical challenges. This presentation dives into the transformative world of NVIDIA DPUs, unveiling how these specialized hardware components are reshaping data center operations.
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Throughout the... -
Alen Arias Vazquez (CERN), Bernard Guncic, Vasileios Amoiridis (CERN)04/10/2023, 14:30
Distributed I/O Tier is a versatile hardware platform for custom electronics in HL-LHC applications within the Accelerators and Technology Sector. This platform exists in two variants: high-performance (non-radiation-tolerant) and radiation-tolerant. The former incorporates the System Board (a.k.a. the crate controller), featuring the Zynq Ultrascale+ MPSoC. This MPSoC runs Linux and provides...
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Dariusz Jakub Zielinski (CERN), Martin Cejp (CERN)04/10/2023, 15:00
The context:
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The Electrical Power Converters group (SY-EPC) is currently in the process of developing the latest iteration of its power converter controller, known as FGC4. It is an embedded device, based on the DI/OT hardware platform, used to control, monitor, and diagnose power converters. The primary control algorithm runs on the system board featuring Xilinx’s Zynq UltraScale+ SoC. The... -
Dominic Ecker (Bergische Universitaet Wuppertal (DE))04/10/2023, 15:50
SoCs are getting adopted extensively by ATLAS systems for the local control and monitoring of their back-end electronics due to their flexibility towards the hardware through the programmable logic but also the convenience provided for higher level software within the Linux platform running on the processing system. The interface to detector control back-end applications is achieved by...
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Younes Otarid (CERN)04/10/2023, 16:20
Caribou is a versatile data acquisition system used by multiple collaborative frameworks (CERN EP R&D, RD50, AIDAinnova) for the qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software base shared accross different projects, thereby drastically reducing the development effort and costs. The current version consists of a...
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Kristin Dona (University of Chicago (US))04/10/2023, 16:50
The Global Feature Extractor (gFEX) is a hardware trigger module that has been recently installed and is in the commissioning process for Run 3 in the ATLAS experiment. The gFEX hardware design includes a Zynq Ultrascale+ SoC used for a variety of purposes. The custom Operating System (OS) used with the SoC is built using the Yocto Project integrated with Xilinx. This talk will discuss updates...
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Andrei Kazarov (University of Johannesburg (SA))04/10/2023, 17:20
We are presenting an update of the prototype implementation of the DAQ to SoC communication library, provided by ATLAS DAQ Online Software group. The presented solution is lightweight, based on the HTTP protocol and Nginx software implementation of HTTP server and allows to organize command exchange between ATLAS Run Control framework and SoC controlled subsystems, typically during operations...
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Giulio Muscarello (Politecnico di Torino (IT))05/10/2023, 10:00
Multiple hardware-platform projects and cooperation on common software features are two topics of interest that have emerged in the System on Chip Interest Group. Based on concrete experience of the ATLAS L1CT group with location-aware booting, we will answer the question “How can PetaLinux achieve this workflow?” by building a PetaLinux project that uses Yocto layers, patch files and device...
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Kareen Arutjunjan (CERN)05/10/2023, 11:20
This tutorial shows how to leverage GitLab CI parallel builds to optimize compilation and testing in PetaLinux projects for several boards simultaneously. Attendees will explore the advantages of enabling Continuous Integration (CI) and Continuous Deployment (CD) for Zynq SoC designs. The main focus is automating compilation, deployment of Zynq PL designs to actual boards, and booting the...
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Nayib Boukadida (Nikhef National institute for subatomic physics (NL))05/10/2023, 13:30
For the readout of ATLAS in LHC Run 4, a prototype readout card was developed; the FLX182. The heart of the design is a Xilinx Versal Prime XCVM1802 device, a SoC with a dual core ARM Cortex-A72 application processor, as well as a Dual-core Arm Cortex-R5F real time processor.
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The board contains 24 bidirectional optical links for DAQ, capable of transferring up to 25 Gb/s of data per link.... -
David Sankey (Science and Technology Facilities Council STFC (GB))05/10/2023, 14:00
This presentation will cover the following aspects:
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- Comparison between Zynq and Versal.
- SoC implementation on Global Common Module (GCM) and its implications managing the file system and OS on multiple boards.
- Module control of FPGA over the Network on Chip (NOC). -
Marvin Fuchs (KIT - Karlsruhe Institute of Technology (DE))05/10/2023, 14:30
In preparation for the High-Luminosity upgrade of the LHC, the Serenity-S1 is designed as a multipurpose ATCA electronics card. Like many other ATCA boards developed for the upgrade, it has a System-on-Chip from the AMD Xilinx Zynq UltraScale+ (ZUS+) family on board. In large systems with hundreds of ZUS+ devices, it is a significant challenge to keep the software on them up-to-date and in a...
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Ralf Spiwoks (CERN)05/10/2023, 15:00
For the Phase-2 upgrade of ATLAS, a new Central Trigger Processor (CTP), new Local Trigger Interfaces (LTIs), and new firmware for the Muon-CTP Interface (MUCTPI) will be developed. Already today, there is an increasing number of modules of prototypes and evaluation boards. All have a System-on-Chip (SoC) and need to be identified and booted with the right boot files, user application software...
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Petr Zejdl (CERN)05/10/2023, 15:50
This presentation will show the latest prototype of DAQ and Timing Hub (DTH) board developed by the CMS DAQ group for the Phase-2 upgrade of CMS. The board has three main functions: Provide data readout of back-end electronics with an aggregated bandwidth of 400 Gb/s over TCP/IP streams towards central DAQ; Interface to the CMS Trigger and Timing Control and Distribution System (TCDS) and...
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Ioannis Bestintzanos (University of Ioannina (GR))05/10/2023, 16:20
An ATCA processor was designed to instrument the first layer of the CMS Barrel Muon Trigger. The processor receives and processes DT and RPC data and produces muon track segments. The control and monitoring of the processor is taking place via a ZYNQ Ultrascale+ SoM. A Linux operating system runs on the ARM processors, providing configuration and monitoring of the board at a higher level....
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Benjamin John Rosser (University of Chicago (US))05/10/2023, 16:50
We present a first look at utilizing the Versal AI Core Series ACAP/SoC for real-time or quasi-real time data processing applications in a high-energy physics context. We start from a demonstration of the LeNet convolutional neural network running on the Versal VCK190 using the AI Engine technology. We then discuss extending this to a more customized network architecture that is potentially...
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Werner Oswaldo Florian Samayoa (Universita e INFN Trieste (IT))05/10/2023, 17:20
The HyperFPGA is an open and scalable SoC-FPGA-based cluster aimed at exploring reconfigurable high-performance computing. HyperFPGA offers a flexible and programmable infrastructure that combines field-programmable gate arrays (FPGAs) with CPUs and high-speed general-purpose connectors. The flexibility of the platform extends to communication protocols at the hardware level, ideal for...
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Michal Husejko (Stanford University (US))06/10/2023, 10:00
This tutorial extends the CI/CD work presented in [1] and [2]. This time we solely focus on automated hardware testing utilizing Kubernetes and container-based infrastructure. First, we start describing an architecture of our testing platform and the device under test (DUT). The platform and DUT considered together combine both x86 and arm64 based hardware nodes. Then we introduce software...
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Christos Gentsos (CERN (IT-CA-GES))06/10/2023, 13:30
Traditionally, FPGA development has been a bit like the Wild West, doing its own thing – separate from modern software practices – but recently there has been a push to incorporate CI pipelines and automated testing and building with version control. This presentation will outline some benefits of adopting CI practices in FPGA/SoC development and, most importantly, announce our plans for an IT...
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Federico Vaga (CERN)06/10/2023, 14:00
The lowest tier in the accelerator control system uses Front-End Computers (x86_64), and in the near future will also feature SoC-based systems (aarch64). For their Operating System, the former use CentOS 7 and are configured as any other PC or server. The latter will likely demand an approach closer to those currently used for embedded systems but, after some research, we could not identify a...
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Alex Iribarren (CERN)06/10/2023, 14:30
The Linux landscape has shifted recently, causing a lot of confusion and nervousness in the community. This presentation will explain the recent changes and how they affect CERN and the wider HEP community, as well as providing an update on the ARM resources offered by CERN IT.
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Brice Copy (CERN), Marc Dobson (CERN)06/10/2023, 15:00
Supply chain attacks in the context of industrial controls involve malicious actors infiltrating the network by exploiting vulnerabilities in third-party components or software used in critical systems. These attacks can compromise the integrity and reliability of industrial operations, potentially leading to disruptions, data breaches, and unauthorized control over essential...
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Diana Scannicchio (University of California Irvine (US)), Marc Dobson (CERN)06/10/2023, 15:45
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Marc Dobson (CERN)06/10/2023, 16:15
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Quentin Duponnois (CERN)06/10/2023, 16:35
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Hamza Boukabache (CERN)06/10/2023, 16:55
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