Speaker
Description
We will describe a novel front end electronics module using a soft-core analog-to-digital converter (ADC) based on time-to-digital converter (TDC). The soft-core ADC is implemented in an FPGA. In the hardware design, the FPGA-based ADC (FPGA-ADC) only requires one resistor and an FPGA. FPGA-ADC allows users to program the sampling rate and adjust the dynamic range of the ADC with small modifications. This design is characterized by flexibility and high density, which can greatly reduce the size of readout circuits for the detector module.
To verify this electronics design, a coincidence PET detector module was built. The detector part used two units. Each unit contained a 3 mm × 3 mm × 10 mm LYSO bar and a SiPM (J-series, from ON Semiconductor). The FPGA-ADC served as the main part of the data acquisition (DAQ) system. It is possible for the FPGA-ADC to perform full waveform sampling on the raw signal of SiPM. The FWHM energy resolution of the two units are 11.2% and 10.5%, respectively. The FWHM coincidence timing resolution of this Prototype is about 385 ps. Besides, a 16-cha FPGA-ADC module is being developed. The implementation and development of the prototype will be reported in the meeting.
