4th 28nm Mixed-Signal Design Workshop

Session

Digital design

13 Dec 2023, 10:15

572/R-006 (CERN)

Presentation materials

28nm-workshop_synthesis_implementation_flat.pdf

17. Digital flow introduction

Erwan Dekhil (Cadence)

13/12/2023, 10:15

Main steps of the flow, tools, Flowkit

6. Single event effects hardening in digital design

Alessandro Caratelli (CERN, EPFL)

13/12/2023, 11:00

38. Timing constraints and synthesis

Erwan Dekhil (Cadence)

13/12/2023, 13:00

39. Lab session (TMR)

Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

13/12/2023, 15:00

40. Lab session (Synthesis and LEC)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

13/12/2023, 15:30

18. Block-level implementation

Erwan Dekhil (Cadence)

14/12/2023, 09:00

Synthesis, floorplan

19. Block-level implementation

Erwan Dekhil (Cadence)

14/12/2023, 10:30

Placement, clock tree synthesis, routing

20. Lab session (Block-level implementation)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

14/12/2023, 13:30

21. Lab session (Block-level implementation)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

14/12/2023, 15:00

22. Hierarchical implementation

Erwan Dekhil (Cadence)

15/12/2023, 09:00

Top level analysis with use of block model, assemble design

41. Lab session (Hierarchical implementation)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

15/12/2023, 10:30

23. Signoff

Erwan Dekhil (Cadence)

15/12/2023, 13:30

Timing analysis, power analysis, DRC, LVS

25. Lab session (Signoff)

Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

15/12/2023, 15:15

24. Lab session

Alessandro Caratelli (CERN, EPFL), Bertrand GENNERET (cadence design systems), Marco Andorno (CERN)