Speaker
Description
We present the design and industrial fabrication of a micro-penning trap.
To fully harness the potential of trapped ions for applications in quantum information processing, it is necessary to scale to large numbers of ions. By building upon existing technologies in micro-fabrication, surface-electrode traps provide a promising approach for a scalable architecture. However, the conventional surface-electrode Paul trap, which relies on strong radio frequency (RF) fields for ion confinement, suffers from limitations such as heat dissipation and restricted connectivity. The recent demonstration of a micro-fabricated surface-electrode Penning trap presents a promising alternative [1]. Penning traps, which operate with a strong, homogeneous magnetic field, eliminate the need for strong RF fields and offer improved ion positioning and connectivity in a three-dimensional trapping region [2].
We present the design of the next generation in micro-fabricated Penning traps, designed for trapping a two-dimensional array of beryllium ions. The trap is split into two zones, a loading zone and a working zone. The loading zone is optimized for creating a deep trapping potential. After an ion is initially trapped in the the loading zone, it is transported into the working zone, where several ions can be brought into close vicinity of each other to perform entangling operations. The design features a planarized multi-metal layer stack on a silicon substrate. The trap is being fabricated in the industrial cleanroom facilities of Infineon Technologies Austria AG in Villach. At the time of writing, the fabrication is ongoing. In the first experiments, we will investigate the transport from the loading zone into the working zone as well as the interaction between ions trapped in separate wells of the trap potential. With these and further experiments, we hope to examine the capabilities of micro-fabricated Penning traps as an alternative to segmented Paul traps in architectures like Quantum CCD.
[1] S. Jain et al. “Unit cell of a Penning micro-trap quantum processor”.
In: (Aug. 2023). DOI: 10.48550/ARXIV. 2308.07672. arXiv: 2308.07672 [quant-ph].
[2] S. Jain et al. “Scalable Arrays of Micro-Penning Traps for Quantum Computing and Simulation”. In: Phys. Rev. X 10 (3 Aug. 2020), p. 031027. DOI: 10.1103/PhysRevX.10.031027. URL: https://link.aps.org/doi/10. 1103/PhysRevX.10.031027.
