Speaker
Dr
Toshinobu Miyoshi
(KEK)
Description
We are developing monolithic pixel detectors in 0.2 um Fully-Deleted SOI
technology. In a SOI wafer, the photodiode is formed on the handling
substrate after removing the silicon oxide. The SOI-CMOS circuits are
fabricated on the 40-nm SOI thin film. Since the bump-bonding process
is not required, a high-gain pixel sensor with smaller pixel size less
than 20 um is achievable. In general SOI-CMOS circuits have less
parasitic capacitance and thus higher speed readout system compared
with bulk-CMOS ones can be composed. Such detectors can be applied
to a wide range of applications, not only in particle physics but also
in medicine, space science and many other disciplines. We have recently
developed several versions of integration-type pixel detectors with
8-17 um pixel sizes. The detectors were irradiated with visible laser,
infrared laser, X-ray and ionizing radiation sources. In this talk,
the recent progress of the detector development, the performance
of the detectors, test results in imaging applications are presented.
Primary author
Dr
Toshinobu Miyoshi
(KEK)
Co-authors
Ayaki Takeda
(SOKENDAI)
Mr
Kazuya Tauchi
(High Energy Accelerator Research Organization)
Mr
Mohammed Imran Ahmed
(AGH University of Science and Technology)
Dr
Piotr Kapusta
(Institute of Nuclear Physics Polish Academy of Sciences)
Dr
Ryo Ichimiya
(High Energy Accelerator Research Organization)
Prof.
Yasuo Arai
(High Energy Accelerator Research Organization (JP))
Mr
Yowichi Fujita
(High Energy Accelerator Research Organization)
Ms
Yukiko Ikemoto
(High Energy Accelerator Research Organization)
