Speaker
Prof.
Kock Kiam Gan
(Ohio State University (US))
Description
We have designed two ASICs for possible applications in the optical links of a new layer of the ATLAS pixel detector for the initial phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for a VCSEL and a receiver/decoder to extract the data and clock from the signal received by a PIN diode. Both ASICs contain 12 channels for operation with a VCSEL or PIN array. Among these channels, the outer four channels are designated as spares to bypass a broken PIN or VCSEL within the inner eight channels. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. With the spacing of 250 μm between two VCSEL or PIN channels, the width of an optical array is only 3 mm. This allows the fabrication of compact parallel optical engine for installation at a location where space is at a premium such as that close to a pixel detector. The fabricated receiver/decoder properly decodes the bi-phase marked input stream with no bit error at low PIN current. The performance of the VCSEL driver at 5 Gb/s is satisfactory. We are able to program the ASICs to bypass a broken PIN or VCSEL and the power-on reset circuits have been successfully implemented to set the ASICs to a default configuration in an event of communication failure. We have irradiated the receiver/decoder to high dose and observe no significant degradation and the SEU rate is low. We plan to irradiate the VCSEL drivers in the summer to measure the radiation hardness. We will present results from the study at the conference. In addition, we will present the design of a new VCSEL driver ASIC to operate at 10 Gb/s which will yield an aggregated bandwidth of 120 Gb/s for a fiber ribbon.
Author
Prof.
Kock Kiam Gan
(Ohio State University (US))
