Conveners
Session5
- Harris Kagan (Ohio State University)
- Minglee Chu (Academia Sinica)
Maurice Garcia-Sciveres
(Lawrence Berkeley National Lab. (US))
05/09/2012, 08:30
Front end electronics and readout - Readout chip developments
ORAL
We present concepts and prototyping results towards a third generation pixel readout chip. We consider the 130nm feature size FE-I4 chip, in production for the ATLAS IBL upgrade, to be a second generation chip. A third generation chip would have to go significantly further. A possible direction is to make the IC so generic that different experiments can configure it to meet significantly...
Dr
Hans-Christian Kaestli
(Paul Scherrer Institut (CH))
05/09/2012, 09:00
Front end electronics and readout - Readout chip developments
ORAL
The performance of the LHC accelerator at CERN has been outstanding since its startup in 2010. It seems likely that the delivered instanteneous luminosity exceeds its design value of $10^{34}$ cm$^{-2} s$^{-1}$ soon after the recommissioning in 2014. Tracking in such a dense environment is challenging. This is especially true for the main tasks of the pixel detector such as b-tagging. In order...
Dr
Martin Van Beuzekom
(NIKHEF (NL))
05/09/2012, 09:20
Front end electronics and readout - Readout chip developments
ORAL
The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the...
Marcel Trimpl
(Fermilab)
05/09/2012, 09:40
Front end electronics and readout - 3D interconnection
ORAL
We describe our current efforts in sensor/electronics integration, including 3D and SOI devices. Application of these technologies to track triggers for CMS and Atlas as well as x-ray imaging will be described. A central question is whether these technologies will be sufficiently affordable with high enough yield to build large area modules such as those required for CMS. We will discuss...
Laura Gonella
(Universitaet Bonn (DE))
05/09/2012, 10:00
Front end electronics and readout - 3D interconnection
ORAL
With the planned upgrades of the LHC for higher than present luminosity, the ATLAS pixel detector will be confronted to higher hit rate. R&D for the inner layers of the future ATLAS pixel detector has started in the direction of smaller feature size CMOS bulk processes, as well as in the direction of the new possibilities offered by 3D integration technologies. In this presentation, a report...
Ms
Eva Vilella-Figueras
(Department of Electronics - University of Barcelona)
05/09/2012, 10:40
Front end electronics and readout - 3D interconnection
POSTER
Geiger-mode avalanche photodiodes (GAPDs) offer excellent qualitites to meet the challenging requirements of the next generation of particle colliders. High sensitivity, fast timing response, virtually infinite gain and compatibility with standard CMOS technologies are some of the properties that make these devices so attractive. In fact, owing to to their extraordinary sensitivity and...
Dr
Kenji Shimazoe
(The University of Tokyo)
05/09/2012, 11:00
Front end electronics and readout - Readout architectures
ORAL
A 144-channel Pr:LuAG-APD detector is designed and fabricated for medical application. The pixel of the crystal is 2mm x 2mm x 10mm and individually coupled with UV-enhanced 12 x 12 Avalanche Photo Diode array. The APD's pixels are individually connected with Time over Threshold based ASIC and sent to DAQ FPGA. ToT-ASIC is fabricated with 0.25um TSMC CMOS and the power dissipation is...
44.
New prototypes for components of a control system for the new ATLAS pixel detector at the HL-LHC
Lukas Pullen
(Uni-Wuppertal)
05/09/2012, 11:20
Front end electronics and readout - Readout chip developments
ORAL
In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerators luminosity by a factor of 10. In the context of this upgrade, the inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of...
Prof.
Kock Kiam Gan
(Ohio State University (US))
05/09/2012, 11:40
Front end electronics and readout - Readout architectures
ORAL
We have designed two ASICs for possible applications in the optical links of a new layer of the ATLAS pixel detector for the initial phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for a VCSEL and a receiver/decoder to extract the data and clock from the signal received by a PIN diode. Both ASICs contain 12 channels for operation with a VCSEL or PIN array. Among...
