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1:45 PM
Tree Tensor Network inference on FPGA
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Lorenzo Borella
(Universita e INFN, Padova (IT))
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2:05 PM
Porting MADGRAPH to FPGA using High-Level Synthesis (HLS)
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Hector Gutierrez Arance
(Univ. of Valencia and CSIC (ES))
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2:25 PM
Transferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger
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David Reikher
(Tel Aviv University (IL))
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2:45 PM
Hardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm
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Mattia Ricchi
(University of Pisa & INFN, Bologna (IT))
Camilla Marella
(University of Bologna)
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3:05 PM
Resource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems
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Timo Muscheid
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3:25 PM
Qibosoq: an open-source framework for quantum circuit RFSoC programming
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Rodolfo Carobene