1st FPGA Developers' Forum (FDF) meeting

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Sessions*

Sharable HDL Cores

Conclusions

Quantum Applications

Introduction

HDL development, verification, and simulation tools

Solutions to everyday digital design problems

Algorithm implementation

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Contributions*

A Neural Network-based trigger for detecting ultra-high-energy neutrinos for RNO-G and IceCube-Gen2 (in session "Algorithm implementation")

Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor (in session "Algorithm implementation")

Assertion-Based Formal Debugging During RTL Development (in session "HDL development, verification, and simulation tools")

Automatic code generation for managing the firmware and software for configuration/status registers and memories in the ATLAS Level-1 Central Trigger (in session "HDL development, verification, and simulation tools")

Becoming vendor agnostic with the help of model-based source code generation (in session "HDL development, verification, and simulation tools")

Best practices to open-source FPGA designs (in session "Introduction")

CERN control group cores and tools (in session "Sharable HDL Cores")

Closing Remarks (in session "Conclusions")

COLIBRI: Towards a CERN-wide common cores library (in session "Sharable HDL Cores")

Convenient and reliable clock domain crossings, using scoped constraints and reusable blocks (in session "Sharable HDL Cores")

Fast Monitoring of FPGA algorithms using SpyBuffers (in session "Sharable HDL Cores")

Fine-grained hierarchical placement constraining for timing closure (and more) (in session "Solutions to everyday digital design problems")

FPGA firmware design and verification for the ATLAS Liquid Argon Calorimeter trigger processor (in session "Solutions to everyday digital design problems")

From C to Routed Circuits for FPGAs in Seconds (in session "Solutions to everyday digital design problems")

Hardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm (in session "Algorithm implementation")

HDL on git (Hog) (in session "HDL development, verification, and simulation tools")

High-Level Synthesis for Machine Learning (in session "HDL development, verification, and simulation tools")

LoCod: an open-source hardware/software co-design tool for SoC/FPGA (in session "HDL development, verification, and simulation tools")

Meeting Photo

Method for achieving phase determinism in the transmission side of AMD transceivers (in session "Solutions to everyday digital design problems")

Open source formal verification with SymbiYosis (in session "HDL development, verification, and simulation tools")

Porting MADGRAPH to FPGA using High-Level Synthesis (HLS) (in session "Algorithm implementation")

Prospects of RFSoC technology in astroparticle physics experiments (in session "Solutions to everyday digital design problems")

Qibosoq: an open-source framework for quantum circuit RFSoC programming (in session "Algorithm implementation")

Registrations

Resource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems (in session "Algorithm implementation")

Summary of 1st FDF meeting (in session "Conclusions")

The BondMachine Project (in session "Sharable HDL Cores")

Transferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger (in session "Algorithm implementation")

Tree Tensor Network inference on FPGA (in session "Algorithm implementation")

Under the Canopy: Exploring Conifer for Low-Latency Decision Forests on FPGAs (in session "HDL development, verification, and simulation tools")

UVVM – An introduction to the world’s fastest growing FPGA verification methodology (in session "HDL development, verification, and simulation tools")

Welcome to CERN (in session "Introduction")

Welcome to the FPGA Developers' Forum (in session "Introduction")

YML2HDL tool (in session "HDL development, verification, and simulation tools")

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Events scheduled on*

11/06/2024

12/06/2024

13/06/2024

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