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12:15 PM
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--- Lunch ---
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1:45 PM
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Algorithm implementation
-Dr
Rui Zou
(Cornell University (US))
Davide Cieri
(Max Planck Society (DE))
(until 3:45 PM)
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1:45 PM
|
Tree Tensor Network inference on FPGA
-
Lorenzo Borella
(Universita e INFN, Padova (IT))
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2:05 PM
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Porting MADGRAPH to FPGA using High-Level Synthesis (HLS)
-
Hector Gutierrez Arance
(Univ. of Valencia and CSIC (ES))
|
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2:25 PM
|
Transferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger
-
David Reikher
(Tel Aviv University (IL))
|
|
2:45 PM
|
Hardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm
-
Camilla Marella
(University of Bologna)
Mattia Ricchi
(University of Pisa & INFN, Bologna (IT))
|
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3:05 PM
|
Resource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems
-
Timo Muscheid
|
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3:25 PM
|
Qibosoq: an open-source framework for quantum circuit RFSoC programming
-
Rodolfo Carobene
|
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3:45 PM
|
--- Tea Break ---
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4:15 PM
|
HDL development, verification, and simulation tools
-
Tom Williams
(Rutherford Appleton Laboratory (GB)) Dr
Nicolo Vladi Biesuz
(Universita e INFN, Ferrara (IT))
(until 6:45 PM)
|
|
4:15 PM
|
High-Level Synthesis for Machine Learning
-
Nicolo Ghielmetti
(CERN)
|
|
4:45 PM
|
Under the Canopy: Exploring Conifer for Low-Latency Decision Forests on FPGAs
-
Sioni Paris Summers
(CERN)
|
|
5:15 PM
|
UVVM – An introduction to the world’s fastest growing FPGA verification methodology
-
Espen Tallaksen
|
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5:55 PM
|
LoCod: an open-source hardware/software co-design tool for SoC/FPGA
-
Florent Manni
(CNES)
|
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7:30 PM
|
--- Dinner ---
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