1st FPGA Developers' Forum (FDF) meeting

from Tuesday, 11 June 2024 (09:00) to Thursday, 13 June 2024 (15:00)
CERN (30/7-018)

        : Sessions
    /     : Talks
        : Breaks
11 Jun 2024
12 Jun 2024
13 Jun 2024
AM
11:00 Registrations   (30/7-018 - Kjell Johnsen Auditorium)
09:00
Solutions to everyday digital design problems - Paschalis Vichoudis (CERN) Filiberto Bonini (CERN) (until 10:45) (30/7-018 - Kjell Johnsen Auditorium)
09:00 Fine-grained hierarchical placement constraining for timing closure (and more) - Alvaro Navarro Tobar (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))   (30/7-018 - Kjell Johnsen Auditorium)
09:25 From C to Routed Circuits for FPGAs in Seconds - Andrea Guerrieri Prof. Andrea Guerrieri (HES-SO and EPFL)   (30/7-018 - Kjell Johnsen Auditorium)
09:45 Method for achieving phase determinism in the transmission side of AMD transceivers - Edoardo Orzes   (30/7-018 - Kjell Johnsen Auditorium)
10:10 Prospects of RFSoC technology in astroparticle physics experiments - Alexander Novikov (University of Delaware)   (30/7-018 - Kjell Johnsen Auditorium)
10:30 FPGA firmware design and verification for the ATLAS Liquid Argon Calorimeter trigger processor - Melissa Aguiar (Federal University of Juiz de Fora (BR)) Marcos Vinicius Silva Oliveira (Brookhaven National Laboratory (US)) Lucca Oliveira Facio Viccini (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
10:45 --- Coffee Break ---
11:15
Algorithm implementation - Davide Cieri (Max Planck Society (DE)) Dr Rui Zou (Cornell University (US)) (until 12:15) (30/7-018 - Kjell Johnsen Auditorium)
11:15 A Neural Network-based trigger for detecting ultra-high-energy neutrinos for RNO-G and IceCube-Gen2 - Pawel Marciniewski (Uppsala University) Mr Pawel Marciniewski (Uppsala University)   (30/7-018 - Kjell Johnsen Auditorium)
11:45 Artificial Intelligence workflows for FPGA & SoC using a Deep Learning Processor - Stephan van Beek (MathWorks)   (30/7-018 - Kjell Johnsen Auditorium)
09:00
HDL development, verification, and simulation tools -Dr Francesco Gonnella (University of Birmingham (GB)) Evangelia Gousiou (CERN) (until 10:45) (30/7-018 - Kjell Johnsen Auditorium)
09:00 YML2HDL tool - Thiago Costa De Paiva (University of Massachusetts (US))   (30/7-018 - Kjell Johnsen Auditorium)
09:20 Automatic code generation for managing the firmware and software for configuration/status registers and memories in the ATLAS Level-1 Central Trigger - Anna Malgorzata Kulinska (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
09:40 Assertion-Based Formal Debugging During RTL Development - N. Engelhardt (YosysHQ)   (30/7-018 - Kjell Johnsen Auditorium)
10:15 Open source formal verification with SymbiYosis - Yann Thoma (HEIG-VD)   (30/7-018 - Kjell Johnsen Auditorium)
10:45 --- Coffee Break ---
11:15
HDL development, verification, and simulation tools -Dr Francesco Gonnella (University of Birmingham (GB)) Evangelia Gousiou (CERN) (until 12:20) (30/7-018 - Kjell Johnsen Auditorium)
11:15 Becoming vendor agnostic with the help of model-based source code generation - Alexander Wirthmüller (MPSI Technologies GmbH)   (30/7-018 - Kjell Johnsen Auditorium)
11:50 HDL on git (Hog) - Nordin Aranzabal Barrio   (30/7-018 - Kjell Johnsen Auditorium)
PM
12:00 --- CERN campus visit ---
14:00
Introduction -Dr Francesco Gonnella (University of Birmingham (GB)) (until 15:10) (30/7-018 - Kjell Johnsen Auditorium)
14:00 Welcome to the FPGA Developers' Forum - Davide Cieri (Max Planck Society (DE))   (30/7-018 - Kjell Johnsen Auditorium)
14:20 Welcome to CERN - Evangelia Gousiou (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
14:40 Best practices to open-source FPGA designs - Javier Serrano (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
15:10 --- Coffee break ---
15:40
Sharable HDL Cores - Mathieu Saccani (CERN) Dr Francesco Gonnella (University of Birmingham (GB)) (until 18:20) (30/7-018 - Kjell Johnsen Auditorium)
15:40 Convenient and reliable clock domain crossings, using scoped constraints and reusable blocks - Lukas Vik (Freelance)   (30/7-018 - Kjell Johnsen Auditorium)
16:20 COLIBRI: Towards a CERN-wide common cores library - Alberto Perro (Universite d'Aix-Marseille III (FR))   (30/7-018 - Kjell Johnsen Auditorium)
16:50 CERN control group cores and tools - Tristan Gingold (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
17:20 Fast Monitoring of FPGA algorithms using SpyBuffers - Iacopo Longarini (University of California Irvine (US))   (30/7-018 - Kjell Johnsen Auditorium)
17:50 The BondMachine Project - Mirko Mariotti (Universita e INFN, Perugia (IT)) Mirko Mariotti (Universita e INFN, Perugia (IT))   (30/7-018 - Kjell Johnsen Auditorium)
18:30 Meeting Photo   (30/7-018 - Kjell Johnsen Auditorium)
12:15 --- Lunch ---
13:45
Algorithm implementation -Dr Rui Zou (Cornell University (US)) Davide Cieri (Max Planck Society (DE)) (until 15:45) (30/7-018 - Kjell Johnsen Auditorium)
13:45 Tree Tensor Network inference on FPGA - Lorenzo Borella (Universita e INFN, Padova (IT))   (30/7-018 - Kjell Johnsen Auditorium)
14:05 Porting MADGRAPH to FPGA using High-Level Synthesis (HLS) - Hector Gutierrez Arance (Univ. of Valencia and CSIC (ES))   (30/7-018 - Kjell Johnsen Auditorium)
14:25 Transferring HLS-generated BDT model into existing firmware in the ATLAS Level-1 trigger - David Reikher (Tel Aviv University (IL))   (30/7-018 - Kjell Johnsen Auditorium)
14:45 Hardware acceleration for fast Magnetic Resonance Fingerprinting map reconstruction: FPGA porting of a deep learning algorithm - Camilla Marella (University of Bologna) Mattia Ricchi (University of Pisa & INFN, Bologna (IT))   (30/7-018 - Kjell Johnsen Auditorium)
15:05 Resource-efficient FPGA implementation of a channelization stage for superconducting quantum detectors DAQ systems - Timo Muscheid   (30/7-018 - Kjell Johnsen Auditorium)
15:25 Qibosoq: an open-source framework for quantum circuit RFSoC programming - Rodolfo Carobene   (30/7-018 - Kjell Johnsen Auditorium)
15:45 --- Tea Break ---
16:15
HDL development, verification, and simulation tools - Tom Williams (Rutherford Appleton Laboratory (GB)) Dr Nicolo Vladi Biesuz (Universita e INFN, Ferrara (IT)) (until 18:45) (30/7-018 - Kjell Johnsen Auditorium)
16:15 High-Level Synthesis for Machine Learning - Nicolo Ghielmetti (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
16:45 Under the Canopy: Exploring Conifer for Low-Latency Decision Forests on FPGAs - Sioni Paris Summers (CERN)   (30/7-018 - Kjell Johnsen Auditorium)
17:15 UVVM – An introduction to the world’s fastest growing FPGA verification methodology - Espen Tallaksen   (30/7-018 - Kjell Johnsen Auditorium)
17:55 LoCod: an open-source hardware/software co-design tool for SoC/FPGA - Florent Manni (CNES)   (30/7-018 - Kjell Johnsen Auditorium)
19:30 --- Dinner ---
12:20
Conclusions - Davide Cieri (Max Planck Society (DE)) (until 12:50) (30/7-018 - Kjell Johnsen Auditorium)
12:20 Summary of 1st FDF meeting - Dr Rui Zou (Cornell University (US))   (30/7-018 - Kjell Johnsen Auditorium)
12:40 Closing Remarks - Dr Francesco Gonnella (University of Birmingham (GB))   (30/7-018 - Kjell Johnsen Auditorium)