Speaker
Description
Depleted Monolithic Active Pixel Sensors (DMAPS) using high-resistivity substrates offer a good signal-to-noise ratio for Minimum Ionizing Particle (MIP) detection as well as an enhanced radiation tolerance with respect to standard CMOS sensors. The fully depleted bulk and fast charge collection through drift enable the DMAPS technology for timing measurements in High Energy Physics (HEP) experiments. In this work, the in-lab calibration and the preliminary test-beam results of a new prototype, mini-CACTUS-V2 will be presented.
Summary (500 words)
The increase of the number of interactions per bunch crossing (pile-up) is one of the experimental challenges in the High Luminosity LHC. ATLAS will be upgraded with a High Granularity Timing Detector (HGTD) in the forward region to mitigate the detrimental effect of pile-up. Mini-CACTUS is a prototype for exploring the possibility of exploiting the Depleted Monolithic Active Pixel Sensors(DMAPS) for timing in High Energy Physics(HEP) experiments. A 65 ps time resolution and an 80 ns recovery time were measured with particle beams.
Encouraged by these promising results, a new prototype, mini-CACTUS_V2, has been designed with LFoundry 150 nm HV technology. The total chip surface is 4.6 x 5 mm2 with different pixel sizes and each pixel features front-end readout electronics, a slow control system whose control data is loaded using an SPI-like bus implementation and an on-chip shift register. The readout electronics are designed between IRFU and IFAE with two new pre-amplifiers to further improve the time resolution and a faster recovery time back to the baseline as well as a new discriminator with programmable hysteresis.
The front-end electronics consists of a pre-amplifier followed by a source follower and a leading-edge discriminator. Each pixel has a 5-bit DAC to adjust the threshold of the discriminator. In this new prototype, two single-ended structures of pre-amplifiers are studied, one employs the structure of Charge Sensitive Amplifier (CSA), and the other of a resistive Trans-Impedance Amplifier (TIA). The performances of the two pre-amplifiers have been simulated with two most interested different pixel sizes: 1 x 1 mm2 (with an equivalent detector capacitance Cd of 1.5 pF) and 1 x 0.5 mm2 (with an equivalent detector capacitance Cd of 1 pF). The dc power consumption is 1.62 mW (95mW/cm2). A jitter of around 40 to 50 ps and a recovery time to the baseline of 25 ns to 30 ns are observed from the post simulation.
The test bench is demonstrated in the picture below: from left to right it consists of a raspberry pi, a GPAC and the DUT. The in-lab calibration is undergoing and the first test-beam is planned by the end of June. In-lab calibration and the preliminary test beam results will be shown at the conference in September.
