22 May 2024
CERN
Europe/Zurich timezone

ALICE ITS3 WAFER-SCALE ON-CHIP READOUT ARCHITECTURE

22 May 2024, 12:36
1m
500/1-001 - Main Auditorium (CERN)

500/1-001 - Main Auditorium

CERN

400
Show room on map

Speaker

Manuel Viqueira Rodriguez (Universidad Politecnica de Madrid (ES))

Description

The ALICE collaboration is developing the new Inner Tracker System 3, a novel detector that uses the stitching technique to construct a single-die monolithic active pixel sensor. For material budget, flexible cables are minimized. This forces all the data to be transferred on-chip to the left edge, responsible for communication with the outside world. These long-distance on-chip communication links require careful optimization of throughput, area, and power consumption. Additionally, the yield must be contained.

To achieve this on-chip readout architecture, the following tasks were performed and will be presented in this contribution:
- Design of a custom DFM standard cells library to achieve the yield.
- Model of the on-chip readout architecture to optimize the various design parameters.
- Create the readout architecture at RTL level.

Primary author

Manuel Viqueira Rodriguez (Universidad Politecnica de Madrid (ES))

Presentation materials