Speaker
Description
Abstract: We present the development of a fully reconfigurable, active-quenching, single photon avalanche diode (SPAD) array. It is fabricated by integrating a bare chip of Field-Programmable Gate Array (FPGA) with a bare die of 4×4 SPAD array with three-dimensional stacked package. The active quenching is realized through the Tri-State Gates and Look-Up Tables (LUTs) of the FPGA. This architecture ensures complete separation of the quenching mechanism from any kind of avalanche photodiode (APD) array (e.g., non-silicon material based APDs), facilitating independent and tailored design of the SPAD array. Compared to a system-on–chip (SOC) based SPAD array, our approach provides a significantly quicker and more flexible deployment, lower startup costs, and is well-suited for developmental stages and lower volume applications.In this study, the SPAD array utilizes an N-on-P design, the pitch of pixels was 60 µm. By setting the dead time of 200 ns and over voltage of 3.2V, it demonstrated afterpulsing rates range from 1.19% to 2.04%, dark count rates range from 93 kcps/pixel to 108 kcps/pixel, crosstalk of 11.8% from the nearest-neighbor pixel and 4.3% from next-nearest-neighbor pixel. It also demonstrated a linear response up to 20MHz. We designed a Time-to-Digital Converter (TDC) for each pixel by employing the same FPGA. These TDCs boast a least significant bit (LSB) ranging from 25.8 ps to 26.3 ps and achieved a time resolution of approximately 1.17 ns for individual pixel under a 532-nm pulse light source. This kind of SPAD array has potential to be applied in fluorescence analysis and transient imaging with great simplicity and flexibility.
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