Speaker
Description
The LHCb Upgrade II, proposed for implementation during Long Shutdown 4 (LS4) of the LHC, aims to operate the detector at a maximum luminosity of 1.5 × 10³⁴ cm⁻²s⁻¹. This necessitates the Upstream Pixel tracker (UP) to achieve a detection efficiency exceeding 99% under extreme hit densities of up to 100 MHz, provide nanosecond-level timing resolution to precisely tag collisions occurring at 25 ns intervals in the LHC, and maintain an average power density below 200 mW/cm². To address these requirements, we propose a monolithic pixel sensors designed in 55 nm HV-CMOS technology. Building on the initial validation of the COFFEE2 prototype, the COFFEE3 chip prototype was designed and submitted for fabrication in early 2025, with delivery expected by late April 2025 for preliminary testing.
The COFFEE3 prototype features two distinct pixel array architectures. This contribution will detail the design innovations, including circuit-level optimizations for timing precision, power management strategies, and architectural trade-offs. Also, the preliminary test results will be reported. The outcomes of this work aim to establish a robust foundation for next-generation radiation-hard, low-power pixel sensors tailored for high-luminosity collider experiments.
| Workshop topics | Front-end electronics and readout |
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