Speaker
Andrew Arzac
Description
We have recently submitted for fabrication PSEC5, an 8-channel mixed-signal waveform-sampling ASIC targeting 1 ps timing resolution, 200 ns buffer length, and multi-hit capability. Here, we describe the architecture and development process of a modular test system for PSEC5. The system consists of two PCBs: a Design Under Test (DUT) Board, and a Control Board. The Control Board is based on the Kria K26 FPGA module. The DUT Board contains PSEC5. The boards are being designed in KiCad; the
FPGA firmware is being written in Vivado. The system has been designed by a team of undergraduates with guidance from experts
Authors
Co-authors
Evan Angelico
Hector Rico-Aniles
(North Central College)
Jinseo Park
Maresa Wynd
(The University of Chicago)
Mary Heintz
(The University of Chicago)
Nathaniel Joseph Pastika
(Fermi National Accelerator Lab. (US))
Paul Michael Rubinov
(Fermi National Accelerator Lab. (US))
Troy England
henry frisch
(university of Chicago)
