Name: 2nd FPGA Developers' Forum (FDF) meeting
Start: 2025-05-20T09:00:00+02:00
End: 2025-05-23T20:00:00+02:00
Location: CERN

2nd FPGA Developers' Forum (FDF) meeting

from Tuesday, May 20, 2025 (9:00 AM) to Friday, May 23, 2025 (8:00 PM)

Monday, May 19, 2025
Tuesday, May 20, 2025

1:00 PM Registrations
Registrations
1:00 PM - 2:00 PM
Room: 500/1-001 - Main Auditorium
2:00 PM
2:00 PM - 3:10 PM
Room: 500/1-001 - Main Auditorium
Contributions

2:00 PM Welcome to the 2nd FPGA Developers' Forum - Davide Cieri (Max Planck Society (DE))

2:20 PM Welcome to CERN - Evangelia Gousiou (CERN)

2:40 PM The future of FPGAs in HEP detectors for FCC and beyond - Sophie Baron (CERN)
3:10 PM Tea Break
Tea Break
3:10 PM - 3:40 PM
Room: 500/1-001 - Main Auditorium
3:40 PM
3:40 PM - 6:30 PM
Room: 500/1-001 - Main Auditorium
Contributions

3:55 PM Open Logic – open-source FPGA Standard Library - Oliver Bründler (OpenLogic)

4:30 PM Unleashing >100G Performance: High-Speed UDP/TCP Hardware Stacks for FPGAs by CAST - Calliope-Louisa Sotiropoulou (CAST)

5:00 PM The PandABlocks framework for flexible run-time configuration of Zynq SoCs - Glenn Christian (Diamond Light Source)

5:25 PM NDK: An open-source framework for high-speed network applications on FPGAs - Daniel Kondys (CESNET) Radek Iša (CESNET)

5:55 PM Error-Redundant Implementation of Commercial IP Cores: A Practical Example - Philipp Jacobsohn (SmartDV)
6:30 PM Group Photo
Group Photo
6:30 PM - 6:45 PM
Room: 500/1-001 - Main Auditorium

6:45 PM Welcome Reception
Welcome Reception
6:45 PM - 8:45 PM
Room: 500/1-001 - Main Auditorium
Wednesday, May 21, 2025
9:00 AM 1
1
9:00 AM - 10:50 AM
Room: 500/1-001 - Main Auditorium
Contributions

9:00 AM Exploring Linearity and Temperature Stability in Time-to-Digital Converters - Gian-Luca Brazerol (Ostschweizer Fachhochschule)

9:30 AM Implementation of Time to Digital Converter on FPGA for high-resolution-performance in Particle Therapy applications - ARASH AMINI BARDPAREH (Politecnico di Torino)

9:50 AM A low latency Gated Recurrent Unit Implementation for the AMD Versal AI Engine - Michail Sapkas (Universita e INFN, Padova (IT))

10:20 AM Where Innovation Meets Reliability – FPGA based solutions by Trenz Electronic - Thomas Brünger (Trenz Electronic GmbH)
10:50 AM Coffee break
Coffee break
10:50 AM - 11:20 AM
Room: 500/1-001 - Main Auditorium
11:20 AM 2
2
11:20 AM - 12:50 PM
Room: 500/1-001 - Main Auditorium
Contributions

11:20 AM Distributed Arithmetic for Real-time Neural Networks on FPGAs - Chang Sun (California Institute of Technology (US))

11:50 AM Chisel4ml: Generating Fast Implementations of Deeply Quantized Neural Networks using Chisel Generators - Jure Vreča (Jožef Stefan Institute)

12:20 PM A Reconfigurable FPGA-Based ML Library for Kernel Methods - Yousef Alnaser (TU Chemnitz, Fraunhofer ENAS)
12:50 PM Lunch
Lunch
12:50 PM - 2:00 PM
Room: 500/1-001 - Main Auditorium
2:00 PM 3
3
2:00 PM - 2:40 PM
Room: 500/1-001 - Main Auditorium
Contributions

2:00 PM Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments - Filip Wojcicki (Imperial College London)

2:20 PM FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems - João Folhadela (Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
2:40 PM 1
1
2:40 PM - 4:00 PM
Room: 500/1-001 - Main Auditorium
Contributions

2:40 PM Abstract interface modelling for better genericity and code clarity - Nicolas Pouillon (Ellisys)

3:10 PM Disruptive Efinix Quantum Architecture - Harald Werner (Efinix Inc.)

3:40 PM Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers - Paul Bachek (Brookhaven National Lab)
4:00 PM Tea Break
Tea Break
4:00 PM - 4:30 PM
Room: 500/1-001 - Main Auditorium
4:30 PM 2
2
4:30 PM - 6:10 PM
Room: 500/1-001 - Main Auditorium
Contributions

4:30 PM CERN ABT's lazy git workflow for equipment-specific designs - Léa Strobino (CERN) Pieter Van Trappen (CERN)

4:50 PM Standardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms - André Pinho (CERN) Irene Degl'Innocenti (CERN)

5:20 PM The new CI4FPGA service at CERN - Christos Gentsos (CERN (IT-CA-GES))
7:00 PM Social Dinner
Social Dinner
7:00 PM - 10:00 PM
Thursday, May 22, 2025
9:00 AM 1
1
9:00 AM - 10:30 AM
Room: 500/1-001 - Main Auditorium
Contributions

9:00 AM Application-Specific Arithmetic Operators with the FloPoCo HDL core generator - Florent de Dinechin (INSA-Lyon)

9:30 AM Customized eFPGAs with FABulous - Dirk Koch (Ruprecht-Karls-Universität Heidelberg)

10:00 AM Allo: A Python-Embedded Programming Model for Composable Accelerator Design - Hongzheng Chen (Cornell University)
10:30 AM Coffee break
Coffee break
10:30 AM - 11:00 AM
Room: 500/1-001 - Main Auditorium
11:00 AM 2
2
11:00 AM - 12:50 PM
Room: 500/1-001 - Main Auditorium
Contributions

11:00 AM Generating memory maps with Cheby and Reksio - Bartosz Bielawski (CERN) Tristan Gingold (CERN)

11:20 AM HDLRegression: A reliable and efficient tool for FPGA regression testing - Marius Elvegård (Inventas)

11:50 AM Common Exchange Format for HDL Build Systems - Lieven Lemiengre (Sigasi)

12:20 PM YosysHQ - Building alternative FPGA toolchains - N. Engelhardt (YosysHQ)
12:50 PM Lunch
Lunch
12:50 PM - 2:10 PM
Room: 500/1-001 - Main Auditorium
2:10 PM
2:10 PM - 2:40 PM
Room: 500/1-001 - Main Auditorium
Contributions

2:10 PM Architecting FPGA for low power Leadership - Hardik Shah (Lattice Semiconductor)
2:40 PM
2:40 PM - 3:50 PM
Room: 500/1-001 - Main Auditorium
Contributions

2:40 PM Enhancing FPGA Verification by Combining VUnit and UVVM - Markus Leiter (P2L2 GmbH)

3:10 PM Get the right FPGA quality through efficient Requirements Coverage (aka Specification Coverage) - Espen Tallaksen (EmLogic)
4:00 PM CERN Campus Visits
CERN Campus Visits
4:00 PM - 6:00 PM
Room: 500/1-001 - Main Auditorium
Friday, May 23, 2025
9:00 AM 2
2
9:00 AM - 10:25 AM
Room: 500/1-001 - Main Auditorium
Contributions

9:00 AM Python-based, flexible testbench for a spacecraft payload - Roberto Rigamonti (HES-SO/HEIG-VD)

9:25 AM Practical Methods for Functional Verification - Simone Ponzio (ARM)

9:55 AM High Performance FPGA Solutions – PRO DESIGN, best Choice for Development and Manufacturing - Bernhard Gleissner (proDesign)
10:25 AM Coffee Break
Coffee Break
10:25 AM - 10:55 AM
Room: 500/1-001 - Main Auditorium
10:55 AM 3
3
10:55 AM - 11:35 AM
Room: 500/1-001 - Main Auditorium
Contributions

10:55 AM Why Your Team Should be using VHDL + OSVVM for Verification - Jim Lewis (SynthWorks)
11:35 AM
11:35 AM - 1:05 PM
Room: 500/1-001 - Main Auditorium
Contributions

11:35 AM Summary of FDF2025 and Awards - Rui Zou (Cornell University (US))

11:55 AM Closing Remarks - Francesco Gonnella (University of Birmingham (GB))

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