|
12:50 PM
|
--- Lunch ---
|
|
2:00 PM
|
Algorithm Implementation
-
Tom Williams
(Rutherford Appleton Laboratory (GB))
(until 2:40 PM)
|
|
2:00 PM
|
Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments
-
Filip Wojcicki
(Imperial College London)
|
|
2:20 PM
|
FPGA Implementation of Next-Generation Reservoir Computing for predicting dynamical systems
-
João Folhadela
(Deutsches Zentrum für Luft- und Raumfahrt e.V. (DLR))
|
|
2:40 PM
|
Solutions to everyday digital design problems
-
Paschalis Vichoudis
(CERN)
(until 4:00 PM)
|
|
2:40 PM
|
Abstract interface modelling for better genericity and code clarity
-
Nicolas Pouillon
(Ellisys)
|
|
3:10 PM
|
Disruptive Efinix Quantum Architecture
-
Harald Werner
(Efinix Inc.)
|
|
3:40 PM
|
Low Jitter Frame Clock Recovery in Xilinx Ultrascale+ Transceivers
-
Paul Bachek
(Brookhaven National Lab)
|
|
4:00 PM
|
--- Tea Break ---
|
|
4:30 PM
|
Solutions to everyday digital design problems
-
Evangelia Gousiou
(CERN)
(until 6:10 PM)
|
|
4:30 PM
|
CERN ABT's lazy git workflow for equipment-specific designs
-
Léa Strobino
(CERN)
Pieter Van Trappen
(CERN)
|
|
4:50 PM
|
Standardizing SoC Development in CERN's accelerator complex: A Build System for Xilinx Platforms
-
Irene Degl'Innocenti
(CERN)
André Pinho
(CERN)
|
|
5:20 PM
|
The new CI4FPGA service at CERN
-
Christos Gentsos
(CERN (IT-CA-GES))
|
|
7:00 PM
|
--- Social Dinner ---
|
