Speaker
Description
The OCTOPUS (Optimized CMOS Technology for Precision in Ultra-thin Silicon)
project, part of the DRD3 collaboration, aims to simulate, develop, and evaluate fine-
pixel monolithic sensors using the 65 nm TPSCo process. The project targets a spatial
resolution of 3 µm, a temporal resolution below 10 ns, a material budget of 50 µm
silicon, and an average power consumption below 50 mW/cm² to meet the needs of
vertex detectors in future lepton colliders.
The OCTOPUS project places significant emphasis on the extensive simulation effort
under Work Package 1, which aims to improve sensor layouts and dimensions. This
includes simulations of standard sensor designs with different readout options and n-
gap designs with small pitch and binary readout. Building on past studies of n-blanket
and n-gap designs, current research also explores ways to improve deep n-implant
geometry. The simulation strategy combines TCAD static simulations and high-statistics
Monte Carlo simulations, both essential for refining sensor designs and improving
performance.
The contribution includes the simulation results for the different pitch standard layout
designs and n-gap layout designs results with varying gap sizes, as well as the
optimization of the n-gap shape.
| Will the talk be given in person or remotely? | In person |
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