Speaker
Description
Machine Learning (ML) techniques are increasingly applied for the optimization of complex computing systems, but their integration into core low-level system mechanisms remains limited. A key barrier is the lack of accessible, high- performance interfaces at the boundary between software and hardware as well as hardware-offloaded ML-inference at full systems speed. In this presentation, we show how Field Programmable Gate Arrays (FPGAs) can be a key enabler for closing this very gap: The combination of mature FPGA shells, thus full-fledged computer systems on reconfigurable fabric, and modern ML compilers for hardware-accelerated inference enables rapid prototyping and deployment of be-spoke ML models directly at the interfaces of key system mechanisms. This approach allows for ultra-low latency, real-time decision making in system components such as memory management, scheduling logic and network control. We outline a vision of the fully ML-optimized FPGA-SmartHub, serving as a research platform for system optimization in both classic computer systems and next-generation accelerators.
