TOPIC Embedded Systems has developed the new CERN ATS SoM Module, which will be presented at this 4th CERN System-on-Chip Workshop. In this presentation, TOPIC shares its expertise in creating Systems-on-Modules based on System-on-Chips and outlines the development process of the new CERN ATS SoM, including the challenges overcome along the way.
In this session we will show how to use the TPM to encrypt and decrypt Linux filesystems for embedded devices. The demonstration will be on AMD's Kria SoM. For encryption the standard LUKS mechanism will be used.
Outline of the presentation/demonstration:
1) Overview of the CRA
A brief introduction to the Cyber Resilience Act and its implications.
2) Why Security Matters: A Practical...
The presentation will discuss the latest updates of the X2O platform for the upcoming Phase-2 upgrade. The X2O platform is a modular system in ATCA standard that includes hardware, firmware and software solutions. Main points/updates of the X2O platform include:
The KRIA SoM (Ultrascale+) as a system controller and IPMC host within the power module (rev.3). Adaptations for VU13P FPGA module...
The L0 Muon Endcap Sector Logic for Phase‐2 upgrade integrates Zynq Ultrascale+ MPSoC with Virtex Ultrascale+ FPGA, interconnected via AXI Chip2Chip. In terms of control and monitoring functionality, the Zynq MPSoC is responsible for the monitoring and control of the ATLAS TGC system through communication with the Virtex FPGA, which provides optical interfaces for approximately 30 front end...
FELIX (FrontEnd LInk eXchange), the readout system designed for ATLAS has been around for some time. Developed since 2012 but taken into operation for ATLAS since 2022, for the ATLAS phase1 upgrade. The first version of FELIX aka phase1 FELIX, was based on a PCIe gen3 card with a Kintex Ultrascale FPGA, not a system on chip. Accessing the various configuration and monitor registers, happens...
Caribou is a versatile data acquisition system used in multiple collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) for laboratory and test-beam qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software stack shared accross different projects, thereby drastically reducing the development effort and cost. It...
AMD’s Versal Gen2 families - AI Edge, Prime, Premium, and RF- deliver adaptive compute, AI acceleration, and advanced connectivity for edge, embedded, networking, and RF applications. In this presentation, we will see how each is purpose-built to meet demanding performance and integration needs, and how this new generation of Versal devices compares with the previous one.
We present a Zynq-7000 system that exploits the full SoC capabilities of both FPGA and CPUs to implement Quantum Key Distribution (QKD) and Quantum Random Number Generation (QRNG) systems. The system can both receive (top->down, Config1) or transmit (down->top, Config2) a data streaming from and to an external source via a TCP. It exploits interrupts, BRAM and bare-metal applications to reach...
The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS detector at the LHC. Its High-Luminosity LHC (HL-LHC) upgrade requires a complete redesign of the readout electronics. The Tile PreProcessor (TilePPr) forms the core of the off-detector system, hosting FPGA-based boards that control and read out the on-detector electronics.
Within the TilePPr, the TileGbE switch...
The Embedded Monitoring Processor (EMP) is a state-of-the-art System-on-Chip (SoC) processing platform developed for the ATLAS Detector Control System (DCS) upgrade. It features a custom baseboard hosting a commercial System-on-Module (SoM) with a Xilinx Zynq UltraScale+ MPSoC. The board exposes a wide range of digital and analog interfaces to support diverse embedded monitoring and control...
The CERN Accelerators and Technologies Sector (ATS) System-on-Module (SoM) project aims to deliver a standardized, high-performance hardware platform for control and data acquisition across CERN’s accelerator complex. Mandated by the Common Controls Technologies Strategy Board (CTSB), the project follows a specification defined by the Common Controls Technologies Technical Board (CTTB). The...
The number of System-on-Chip (SoC) applications in the accelerator complex at CERN is rising. This motivated a survey of SoC users within CERN's ATS, and a study to identify generic architectures, common needs for services, and ways of integrating SoCs in the accelerator control system. The outcome of the study is the ATS SoC Framework project, which is developing a framework with common tools...
The future HL-LHC Beam Position Monitor (BPM) data acquisition system to be installed near the ATLAS and CMS experiments is an application with demanding digitization and signal processing requirements. The system development has progressed since last presented at the SoC Workshop in 2023. The talk will start with a refresh of the project requirements and background followed by a discussion of...
The TriglaV ASIC is a RISC-V-based SoC designed to address the requirements of future particle physics experiments. Fabricated in a TID-robust 28nm CMOS technology, it integrates fault-tolerance against single-event effects using TMR and ECC techniques. The architecture features a triplicated core, ECC-hardened memory blocks, hardened peripherals and interconnects. TriglaV was built via the...
We’ll do a 2-part presentation; First a few pointers for analyzing features of an RF enabled SoM “how to choose an RF-SoM for best performance” followed by a deep-dive into “low jitter clocking architectures for RF-SoMs” where we will share our recent advances in clock designs, learnings and design pitfalls to avoid.
This talk presents a comprehensive methodology for achieving robust testability in CROME, a heterogeneous system-on-chip (SoC) platform engineered for safety-critical application. CROME combines custom IP cores, multiple processor subsystems, and a pseudo real-time software components into a tightly coupled hardware-software ecosystem. Due to the system’s architectural heterogeneity and...
CRAZy ("Compact Remote Administration for Zynq") is a minimalistic implementation of IPMI/RMCP protocols running in the ZynqMP's Power Management Unit (RMCP). It provides a remote reset and serial console capability that runs completely independently from the APUs (Cortex-A cores) and can be fitted to most ZynqMP-based platforms without any need for hardware modifications.
This contribution presents our experience deploying containerised control applications on System-on-Chip (SoC) platforms as part of the CMS Phase-2 Data Acquisition (DAQ) system upgrade. Specifically, we evaluate the use of Kubernetes on a Xilinx Kria K26 SoM (Zynq UltraScale+ MPSoC), which provides embedded control and monitoring for the DAQ and Timing Hub (DTH400) and DAQ800 boards. We...
DAQ-to-SoC communication library aims to help integration of SoC systems in ATLAS data-taking environment: it allows a DAQ application to exchange commands and data with a server application running on SoC.
The implementation is based on HTTP protocol and client sends commands and payload to a server using HTTP POST requests and gets back a response including a response code plus arbitrary...
Modern System-on-Chip (SoC) devices tightly integrate advanced components such as multi-core processors, AI accelerators, Field-Programmable Gate Array (FPGA) fabric, and high-speed interfaces into a single package, thereby promising to solve demanding challenges across various industries through heterogeneous computing at the edge. However, the increasing complexity of these systems comes at...
Our talk will cover recent developments and current plans for Embedded Linux and applications on SoC devices in the APx environment. The APx environment supports a family of FPGA cards in the ATCA form factor, for trigger processing and DAQ readout in the CMS detector. We will discuss how we build and deploy linux and firmware images and configuration. We will discuss our tools and...
Presentation will include:
1. Setting up a lightweight k3 Kubernetes cluster which is build out of the Aarch64 (AMD/Xilinx Versal Gen1 dev kits) and x86_64 (VMs) nodes.
2. Setting up gitlab CI/CD pipelines to build firmware, Petalinux (or Yocto), and an example software using the above cluster.
3. Setting up gitlab CI/CD pipelines to deploy to the cluster all the components in the automated...
The TDAQ System Administration team manages the installation and configuration of the Operating System (OS) of all the nodes of the ATLAS experiment and of the ATLAS TDAQ TestBed Laboratory in the CERN General Purpose Network. The currently supported OS is AlmaLinux 9 and it can be installed locally or via network.
Some of the SoC devices (e.g Zynq MPSoc) can be booted with that supported OS...
The new CMS DAQ electronics for the Phase-2 upgrade are equipped with a ZYNQ MPSoC on the Rear Transition Module (RTM). These ZYNQ MPSoCs are fully network-booted. We present the implementation of the network booting mechanism and its configuration using the DHCP Client ID for geographical addressing within the ATCA chassis. Additionally, we describe the containerized network services running...
In the ATS sector, the Xilinx Zynq UltraScale+ MPSoC is deployed on the DIOT platform as a versatile solution. However, its general-purpose nature results in multiple BOOT.BIN files for various applications. To manage this complexity and ensure a reliable boot process across different use cases, we developed a two-stage boot mechanism. This method first initializes a common golden BOOT.BIN,...
The System Administration and networking aspects for supporting the embedded controllers in the ATLAS experiment will be described. Various aspects will be covered such as the network architecture options and restrictions and the operating system (OS) support, management and booting process (the details of which are covered in dedicated presentations).
Most information will be common to both...
