9. Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

19 May 2026, 15:38
1m
Patio and Auditorium Hall (CICSU)

Patio and Auditorium Hall

CICSU

Centre de conférences internationales - Sorbonne Université 4 Place Jussieu, 75005 Paris

Speaker

Olivier Salin (Université Paris-Saclay)

Description

The High-Luminosity LHC is set to begin operations for physics around 2030, enabling the collection of ten times more data than will have been accumulated by the LHC. The resulting increase in pile-up, radiation exposure, and data volume requires a comprehensive upgrade of both the on‑detector and off‑detector electronics of the ATLAS Liquid Argon (LAr) Calorimeter to maintain excellent energy and timing performance within the new trigger and data acquisition architecture.

On-detector, the complete replacement of the Front-End Boards (FEBs) and Calibration Boards is in progress. The redesigned FEBs amplify, shape, and digitize calorimeter ionization signals at 40 MHz using two gain scales, achieving an effective 16‑bit dynamic range with 11‑bit precision. This is enabled by custom radiation‑hard Preamplifier/Shaper and ADC ASICs. The new Calibration Board injects precision pulses with <0.1% non-linearity, 0.25% inter‑channel variation, and rise times below 1 ns, using two dedicated ASICs (LADOC and CLADOC). Prototype boards and ASIC test procedures are in advanced validation ahead of large‑scale production of approximately 1,500 units, scheduled to be installed starting 2027.

Off‑detector, the upgraded digital processing chain is built around the ATCA‑compliant Liquid Argon Signal Processor (LASP). Each of the 278 LASP modules receives 40 MHz digitized samples over 33,000 optical links, totalling 345 Tbps. Two high‑performance Agilex FPGAs per module execute real‑time energy and time reconstruction, forwarding low‑latency energy sums to the hardware trigger while buffering the full data stream pending trigger acceptance. To address the significantly increased pile‑up, advanced neural‑network‑based reconstruction algorithms are being implemented in firmware to separate overlapping pulses. Data transmission to the acquisition system is handled by the Smart Rear Transition Module, while system timing and control of up to 72 on‑detector boards is provided by the compact LATOURNETT board.

This contribution presents the integrated architecture, performance validation, and latest hardware and firmware developments across the full LAr calorimeter electronics upgrade for HL‑LHC operation.

Track Upgrades

Author

Olivier Salin (Université Paris-Saclay)

Presentation materials