Speaker
Description
An RPC detector stack of 12 layers is operational at TIFR, Mumbai. A cosmic muon veto detector (CMVD) is under development around the RPC detector. This is part of a study to assess the feasibility of constructing a shallow-depth neutrino detector. The CMVD employs extruded plastic scintillator (EPS) strips as the active medium. Muon interactions within the EPS are registered by silicon photomultipliers (SiPMs) coupled to two wavelength-shifting fibres embedded in each strip.
The system is being designed to achieve a muon detection efficiency exceeding 99.99%. Reliable muon identification necessitates precise measurement of the SiPM charge output. The analogue signals from the SiPMs are converted into voltage pulses using trans-impedance amplifiers and subsequently sampled by a DRS4 chip operating at 1 GS/s. The samples are digitised using a fast ADC. Signal sampling and digitisation is initiated upon receiving the cosmic muon trigger in the RPC stack, after which the data are zero-suppressed and transmitted to a back-end server. The back-end can further analyse the waveform samples to ascertain the charge of the SiPM signal.
Data acquisition control is implemented on an AMD Spartan-7 FPGA, hosting a MicroBlaze soft-core processor for process management. The FPGA-based DAQ board under design integrates five DRS4 ASICs along with a network interface. A 32-channel board consisting of 4 DRS4 chips, an AMD FPGA and a network interface is being designed. This paper describes the prototype development of the SiPM waveform digitising readout board incorporating the DRS4 ASIC and Spartan-7 FPGA.
| Position | Scientific Officer |
|---|---|
| Affiliation | Tata Institute of Fundamental Research |
| Country | India |