Speaker
Description
The current ATLAS Inner Detector will be upgraded to an all-silicon Inner Tracker (ITk) for the Phase 2 upgrade of the experiment.
The innermost part of the ITk will consist of about 10k pixel modules, totaling more than 5 gigapixels that should be controlled and read out by the upgraded DAQ system.
The basic read-out chain includes a PC sever hosting a dedicated PCIe FPGA-based board (FELIX) that provides the interface between the back-end DAQ software (ITkSW) and database on one side, and the on-detector hardware on the other side.
On the detector side, FELIX provides 24 bidirectional high-speed links through which the configuration and control commands are sent to the front-ends on the downlink.
The on-detector optobox performs optoelectrical conversion of these signals and distributes the data to the front-end chips (ITkPix) via the lpGBT aggregator ASIC at 160 Mbps.
The hit data response is output at 1.28 Gbps and again bundled by the lpGBT into the uplink high-speed link at 10.24 Gbps, to arrive back in FELIX for processing by the ITkSW.
To develop and test the read-out chain building blocks, we proposed an FPGA-based platform that can replace all the on-detector complex hardware parts through intensive utilisation of hardware emulators of the front-ends and lpGBTs.
The first version was implemented on two FPGA development boards allowing to fully populate the FELIX 24-fiber links.
To benefit from the existence of extra FELIX boards and their software tools, a second version (named FELIG-Pixel) was developed using the very same FELIX Phase-1 board, with the ITkPixV1 and ITkPixV2 front-end emulator choices made available.
In particular, this includes modelling different module configurations, where in the extreme cases either 4 ITkPix chips share one uplink lane, or where one ITkPix chip occupies 4 uplink lanes, to adapt the bandwidth to the data rate requirements.
A complete ITk-Pixel read-out chain can be thus built with two FPGA boards (FELIX and FELIG) in one or two servers, simply connected by fiber trunk cables, which provides a valuable asset for the Phase-2 ITk DAQ system development.
The FELIG firmware is included in the FELIX firmware distribution, where it uses common code shared with the data generator designs of other subdetectors, such as ITk Strips.
Such a set-up was demonstrated and installed at CERN where DAQ developers can access it remotely through an on-line booking system. The versatility of this FPGA-based solution allows adding other test use cases during the Phase-2 ITkSW development but also data taking later.
| Position | PhD Student |
|---|---|
| Affiliation | II. Physikalisches Institut, Georg-August-Universität Göttingen |
| Country | Germany |