2–6 Feb 2026
TIFR, Mumbai
Asia/Kolkata timezone

LIGHT01: A prototype LGAD pixel readout ASIC with ps timing resolution in 28 nm technology

5 Feb 2026, 14:45
15m
TIFR, Mumbai

TIFR, Mumbai

Tata Institute of Fundamental Research, Homi Bhabha Road, Navy Nagar, Colaba, Mumbai 400005, India
Oral Fast and precise timing devices Parallel Session-IV

Speaker

GHIMOUZ, Abderrahmane (Paul Scherrer Institute (CH))

Description

We present LIGHT01 (LGAD-based Integrated Granular Hybrid Timing ASIC), the first prototype in a new family of dedicated readout chips for Low Gain Avalanche Detector (LGAD) pixels. LIGHT01 implements an $8 \times 8$ pixel matrix with fully independent channels, each comprising a preamplifier optimized for LGAD capacitances, a fast discriminator, and a time-to-digital converter (TDC), with a target per-channel time resolution of 30ps. Designed in TSMC 28nm technology, the ASIC has undergone detailed post-layout simulations, demonstrating initial performance in terms of noise, jitter, and power consumption. First silicon is expected from fabrication in early 2026, with a complete test bench already prepared for rapid characterization. We also discuss the hybrid integration strategy with LGAD sensors and the roadmap for future iterations, aiming toward scalable, low-power, and radiation-tolerant architectures suitable for large-area timing systems, with potential application in future upgrades of the CMS detector and other collider experiments.

Position PostDoc
Affiliation Paul Scherrer Institut (PSI)
Country Switzerland

Author

GHIMOUZ, Abderrahmane (Paul Scherrer Institute (CH))

Co-authors

EBRAHIMI, Aliakbar (Paul Scherrer Institute (CH)) HANS-CHRISTIAN, Kaestli (PSI) MEIER, Beat (Paul Scherrer Institute (CH)) PIQUE, Noah (Paul Scherrer Institute (CH))

Presentation materials