Speaker
Description
In the coming years, the LHCb Ring Imaging Cherenkov (RICH) sub-detectors will go through a major upgrade of its opto-electronics architecture as part of the LS3 Enhancement and Upgrade II programs. Due to the prompt nature of Cherenkov radiation, photons from a single track reach the Photon Detector planes with a spread of ~10 ps. The introduction of time tagging capabilities in the RICH system will allow to further improve the LHCb particle identification and will serve as a key pathfinder for the entire LHCb Upgrade II programme. The new electronics will be redesigned to operate with time resolutions which are better than 100 ps, with higher data bandwidths, and should achieve better granularity with smaller sensor elementary cells.
The core of the next generation of RICH fast-timing readout chains is a novel ASIC, the FastRICH, that was designed to meet the requirements of the RICH single-photon electronics chain. The ASIC design is a collaboration effort between CERN and University of Barcelona and includes a radiation-hard integrated circuit with digital-on-top design implemented in a 65 nm CMOS technology node. It features 16 input channels that can work either in positive or negative polarity. Its input dynamic range is between 50 μA to 5 mA, which allows the coupling to various single-photons sensitive devices such as: MaPMTs, silicon photomultipliers (SiPMs), or micro-channel plates sensors (MCPs). A built-in TDC with 24.41 ps bins and auto-calibration capabilities is used inside the chip. It allows measurements of TOA with 24.41 ps per bin and of time-over-threshold (TOT) with bins of 390.62 ps - up to a maximum range of 100 ns. The output of the TDC is filtered through a digital gate that has configurable start time in 195.32 ps steps. The maximum width of the gate is 6.25 ns and it can be configured in steps of 24.41 ps. To transmit the data, a data-driven readout protocol is used to dynamically adapt to the hits arriving in the same event. The commercial Aurora 64b/66b protocol is used to encode the data stream and to send it through serializers with a configurable speed between 0.32 Gbps and 5.12 Gbps. The FastRICH chip will be packed in a 10 mm x 10 mm plastic molded QFN88 package. The overall power consumption has been optimized to be less than 16 mW/channel with the ASIC powered at 1.2 V nominal voltage.
The ASIC was received from the foundry in May 2025, and considerable effort was already devoted to evaluating the prototypes using various test benches. This covers both single-ASIC and multi-ASIC tests. A prototype RICH LS3 Enhancements photo-detector module is being produced to integrate multiple ASICs in a close-to-real readout architecture, and it is foreseen that it will be used in the lab and in future test-beam campaigns at CERN PS/SPS facilities. The module comprises several components which build a ready-to-use system and will introduce new ASIC technologies, lpGBT and VTRX+ for data transmission and slow control and bPOL12V for providing power.
The FastRICH prototype validation and its proposed electronic readout chain are a very important milestone to reach for the future RICH upgrade programs. Single ASIC tests have been successfully carried out in the lab and the first results will be presented. An irradiation qualification campaign is currently undergoing to test the ASIC in radiation environments with very high total ionizing dose (TID), and we aim to extract the probability of single-event-effects (SEEs) in the chip. Results from the ASIC validation campaign and the actual progress on the prototype readout electronics design tests will be presented for the R&D program connected to this LS3 Enhancement of the LHCb RICH detectors.
| Position | Senior Researcher |
|---|---|
| Affiliation | National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO) |
| Country | Romania |