Speaker
Description
Experiments and applications such as High Energy Physics, Particle physics, Muon Tomography, Positron Emission Tomography (PET) and Light Detection and Ranging (LIDAR) require data acquisition (DAQs) systems with large number of readout channels. A multi-channel and high-resolution Time-to-Digital Converter (TDCs) is also an integral part of the DAQ system of such applications. Optimizing the space, power consumption and throughput performance of the DAQ system is an essential requirement of these applications. In a System-on-Chip (SoC) approach, these performance matrices can be achieved by integrating the DAQ logic with microprocessor and data transfer protocol inside a single chip like FPGA.
Thus, a high resolution TDC was developed and interfaced with MicroBlaze processor in FPGA through the Advanced eXtensible Interface (AXI) bus. The bus is used as a memory mapped interface between the processor and the peripherals. The TDC was built using Flash based architecture [1][2], consisting of coarse and fine measurements. The coarse time was measured using a counter operating at 200 MHz (time period ~ 5 ns), and the fine time within one clock period was measured using a delay line. Eighty delay cells in a delay line are required in the Artix-7 FPGA for fine time measurement within one clock period of 5 ns, resulting in a Least Significant Bit (LSB) resolution of 62 pico-seconds (ps). The TDC was characterized using a commercial delay generator up to 40 µs dynamic range. The measured values of single-shot precisions were less than 50 ps across the dynamic range of the TDC. For the data transfer, the UART AXI peripheral was interfaced with the MicroBlaze processor system. This SoC approach was tested in a commercial AMD AC701 development board.
The paper presents the implementation details of a high resolution TDC integrated with a microprocessor and data transfer protocol in a single AMD Artix-7 FPGA with efforts for further improvements of TDC resolution (LSB) to sub 50 ps and integrating it with high speed 1Gbps Ethernet interfaces in a FPGA.
| Position | Scientific Officer-G |
|---|---|
| Affiliation | Bhabha Atomic Research Centre |
| Country | India |