Speaker
Description
The design and status of developing the Level-0 endcap muon trigger firmware of
the ATLAS experiment at HL-LHC are reported. An ATCA blade with an XCVU13P FPGA
and the firmware to identify muon candidates have been developed. The firmware
uses detector hits from the Thin Gap Chambers (TGC) to reconstruct candidates
and takes the coincidence with data from other inner muon detectors, called
Inner Coincidence, to reject fake backgrounds. The Inner Coincidence logic and
the coincidence pattern were implemented and validated using inputs from TGC
and inner muon detectors. The consistency of the logic outputs was confirmed by
extensive tests with test patterns. Furthermore, a new verification system
utilizing FPGA accelerator cards equipping similar resources was developed to
support efficient trigger logic development. This poster will report the
concept of the inner coincidence, the actual design, the methodology of
validation, and resource usage in the implementation phase. Also, a dedicated
discussion will be given on developing and designing the FPGA accelerator
card-based validation system.
| Position | TBC |
|---|---|
| Affiliation | TBC |
| Country | TBC |