Speaker
Description
The ATLAS Liquid Argon (LAr) calorimeter readout electronics will be fully
upgraded for operation at the High-Luminosity LHC (HL-LHC), where up to about
200 proton-proton interactions per bunch crossing will impose stringent
requirements on radiation tolerance, bandwidth, and signal reconstruction
performance. The upgraded system is designed to maintain the excellent energy
and timing resolution of the detector under these challenging conditions.
The new on-detector readout electronics are based on second-generation
Front-End Boards (FEB2) installed on the calorimeter cryostat
feedthroughs. Each board reads out up to 128 calorimeter channels and performs
amplification, shaping, digitization, and serialization of the detector
signals before transmitting the data to the off-detector processing system
through high-speed optical links. In total, the system continuously reads out
182,468 calorimeter channels at the 40 MHz bunch-crossing rate.
The off-detector processing is performed by the LAr Signal Processor system
implemented as ATCA boards equipped with high-performance FPGAs and high-speed
optical interfaces. These boards receive digitized samples from the
on-detector readout electronics through optical links and reconstruct the
deposited energy and timing for each calorimeter channel in real
time. Reconstructed quantities are transmitted with low latency to the
hardware trigger system, while the full data stream is buffered and forwarded
to the data acquisition system after trigger accept signals. The upgraded
readout architecture also includes a dedicated timing and control system
responsible for distributing clock, trigger, and configuration signals to the
on-detector electronics and monitoring the operation of the readout chain.
LHC Run 3 will conclude at the end of June 2026, after which the ATLAS
detector will enter Long Shutdown 3 (LS3) to prepare for the HL-LHC
upgrade. Custom ASICs are currently in production and testing, and several
generations of FEB2 prototype boards have been developed and
characterized. Prototype signal-processing boards and demonstrator firmware
have been tested in integration setups combining on-detector electronics,
timing distribution, and data acquisition components. System integration
tests combining on-detector electronics with timing, control, and off-detector
processing systems are ongoing. Installation of the new off-detector readout
system is planned to begin in mid-2027, while installation of the on-detector
electronics is planned to start at the end of 2027, followed by extensive
system commissioning.
This contribution will present the design and performance of the upgraded
on-detector and off-detector readout electronics, the results of prototype and
integration tests.