Speaker
Description
The upgrade of the ATLAS Liquid Argon (LAr) calorimeter readout electronics for the High-Luminosity LHC (HL-LHC) introduces a new off-detector processing architecture designed to handle the extreme data rates and pileup conditions expected during HL-LHC operation. Continuous digitization of all calorimeter channels at the 40 MHz bunch-crossing rate will produce data streams corresponding to several hundred terabits per second, requiring large-scale real-time processing while maintaining the low latency required by the ATLAS trigger system.
The off-detector processing is performed by the LAr Signal Processor system implemented as ATCA boards equipped with high-performance FPGAs and high-speed optical interfaces. These boards receive digitized samples from the on-detector readout electronics through optical links and reconstruct the deposited energy and timing for each calorimeter channel in real time. Reconstructed quantities are transmitted with low latency to the hardware trigger system, while the full data stream is buffered and forwarded to the data acquisition system after trigger accept signals.
The upgraded readout architecture also includes a dedicated timing and control system responsible for distributing clock, trigger, and configuration signals to the on-detector electronics and monitoring the operation of the readout chain.
Signal reconstruction must operate in an environment where pulses from multiple bunch crossings overlap. While optimal filtering techniques are currently used in ATLAS calorimeter readout, machine-learning-based reconstruction approaches are being investigated as complementary solutions. Neural-network algorithms optimized for FPGA implementation show improved robustness against pileup and distorted pulse shapes while satisfying strict latency and throughput constraints.
LHC Run 3 will conclude at the end of June 2026, after which the ATLAS detector will enter Long Shutdown 3 to prepare for the HL-LHC upgrade. Prototype signal-processing boards and demonstrator firmware have been tested in integration setups combining on-detector electronics, timing distribution, and data acquisition components. Installation of the off-detector readout system is planned to begin in mid-2027.
This contribution will present the architecture of the upgraded off-detector readout system, results from prototype and integration tests, and the status of real-time reconstruction developments for HL-LHC operation.