10–14 Nov 2025
CERN
Europe/Zurich timezone

Advancements and future expansions of the Caribou DAQ system

13 Nov 2025, 12:30
20m
31/3-004 - IT Amphitheatre (CERN)

31/3-004 - IT Amphitheatre

CERN

105
Show room on map
WG5 - Characterization techniques - facilities WG5 - Characterization techniques, facilities

Speaker

Younes Otarid (CERN)

Description

Caribou is a versatile data acquisition (DAQ) system developed within several collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, and Tangerine) to support laboratory and test-beam characterization of novel silicon pixel detectors. It combines a custom Control and Readout (CaR) board with a Xilinx Zynq System-on-Chip (SoC) running project-wide shared firmware and software stacks. The system architecture emphasizes reusability, flexibility, and ease of integration.
The CaR board provides essential interfaces such as programmable power supplies, voltage and current references, high-speed ADCs, and configurable I/O lines for detector control and readout. The SoC runs an embedded Linux distribution built with PetaLinux and integrates two main components: Peary, a C++ embedded DAQ application providing hardware abstraction, configuration management, logging, and multi-device control through Command Line (CLI) and Python interfaces; and Boreal, a common Caribou FPGA firmware framework offering reusable modules and automated build workflows for user-specific bit files.
The next major milestone in Caribou’s evolution is the transition to version 2.0, based on a Zynq UltraScale+ System-on-Module (SoM) architecture. Compatibility with UltraScale+ MPSoC evaluation platforms such as the AMD ZCU102 and the Enclustra Mercury+ ST1/XU1 has already been demonstrated, paving the way for the integration of the SoC directly onto the CaR board and the removal of external evaluation platforms.
Recent progress in the Caribou project includes the development of a test bench for CaR board v1.5 validation and first results from a dedicated test board that was developed to validate components for the future CaR board v2.0. In parallel, the Peary embedded application architecture is being revised to support multiple boards and platforms, and some of the Boreal FPGA firmware modules are being migrated to the UltraScale+ platform. This presentation will provide an overview of the current status, recent progress and future prospects of the project.

Type of presentation (in-person/online) in-person presentation
Type of presentation (I. scientific results or II. project proposal) I. Presentation on scientific results

Author

Co-authors

Changbum You (Carleton University (CA)) Dominik Dannheim (CERN) Eric Buschmann (Brookhaven National Laboratory (US)) Hucheng Chen (Brookhaven National Laboratory (US)) Ilias Kamoisis (CERN and Aristotle University of Thessaloniki (GR)) Mathieu Benoit (Oak Ridge National Laboratory (ORNL)) Ryan St-Jean (Carleton University (CA)) Shaochun Tang (Brookhaven National Laboratory (US)) Simon Spannagel (Deutsches Elektronen-Synchrotron (DE)) Thomas Koffas (Carleton University (CA)) Tomas Vanat (Deutsches Elektronen-Synchrotron (DE))

Presentation materials