Speaker
Description
The OCTOPUS (Optimized CMOS Technology for Precision in Ultra-thin Silicon) project, part of the DRD3 collaboration, aims to develop Monolithic Active Pixel Sensors (MAPS) based on the TPSCo 65 nm CMOS process, designed to meet the key requirements of vertex detectors operating in the next generation of lepton colliders.
The sensor development is planned in two stages. The first large-area prototype will be a 50 µm-thick beam telescope demonstrator, targeting a spatial resolution of 3 µm, a hit rate capability of approximately 100 MHz/cm², a time resolution of 100 ns, and an average power consumption below 500 mW/cm². The final chip — a 50 µm-thick, full-reticle vertex detector demonstrator — aims to achieve a time resolution of 5 ns and an average power consumption below 50 mW/cm², while maintaining the 3 µm spatial resolution.
The project brings together 13 European institutes involved in a broad range of R&D activities, including sensor layout design and optimization using TCAD modeling and Monte Carlo simulations, ASIC design and verification, DAQ development for prototype testing, and sensor characterization to validate performance against project requirements.
This contribution presents an overview of the project, with a focus on the modeling and design of the readout architecture concepts for the first pixel sensor prototype.
| Type of presentation (in-person/online) | in-person presentation |
|---|---|
| Type of presentation (I. scientific results or II. project proposal) | I. Presentation on scientific results |
