4th DRD3 week on Solid State Detectors R&D

Session

WG/WP1 - CMOS technologies

10 Nov 2025, 14:15

6/2-024 - BE Auditorium Meyrin (CERN)

Conveners

WG/WP1 - CMOS technologies: Scintific results from WPs

• Heinz Pernegger (CERN)
• Eva Vilella Figueras (University of Liverpool (GB))
• Jerome Baudot (IPHC - Strasbourg)

37. First results of COFFEE3, a small prototype for 55nm HVCMOS validation

Zijun Xu (Chinese Academy of Sciences (CN))

10/11/2025, 14:15

WG1 - Monolithic Sensors

The HVCMOS technology is promising technology for tracking detectors at future experiments such as LHCb upgrade and Higgs factories, for its radiation hardness, fast charge collection and hence good spatial and timing resolution. Development of HVCMOS in smaller feature size will allow more functionailities in the same pixel area, and a reduced power consumption. We proposed a project to...

53. DRD3 Community Shared Submission in LF15A Technology

Eva Vilella Figueras (University of Liverpool (GB))

10/11/2025, 14:35

WG1 - Monolithic Sensors

We are organising a DRD3 community shared submission in the 150 nm High Voltage CMOS process (LF15A) from LFoundry. This joint submission will include several chips designed by the DRD3 community to further advance the R&D of High Voltage CMOS sensors for future detector applications in physics experiments. By sharing the wafer among several chips with compatible requirements, this...

55. Testbeam results of the MiniCactus V2 timing demonstrator

Joaquim Pinol Bel (IFAE)

10/11/2025, 14:55

WG1 - Monolithic Sensors

MiniCactus V2 is a demonstrator intended to study the timing performance that can be obtained from non amplified large electrode CMOS sensors developed with the 150 nm LFoundry HV CMOS LF15A technology.

MiniCactus V2 is the most recent iteration of a line of timing oriented sensors, with improved performance over its predecessors. It features pixels of different sizes, from 1mm x 1mm to 0.5...

56. Development of sensors with intrinsic gain in LFoundry 150 nm technology

Prof. Philippe Schwemling (Université Paris-Saclay (FR))

10/11/2025, 15:15

WG1 - Monolithic Sensors

One of the limitations of monolithic sensors is their signal over noise ratio, which constrains strongly the downstream front-end electronics, especially for timing oriented sensors, and leads to architectures that are quite power hungry. Present monolithic designs have been shown to reach a 50 ps time resolution for MIPs, with a power consumption of several hundreds of mW per $cm^2$.

A...

74. Status on access and submission preparation for MAPS technologies within DRD7.6a

Walter Snoeys (CERN)

10/11/2025, 15:35

WG1 - Monolithic Sensors

Report on the activity within DRD7.6a project to prepare submissions in the TPSCo 65 nm technology. Status of the possible IP sharing and run schedule will be discussed.

66. Recent measurements on the CASSIA1 sensors

Anastasia Kotsokechagia (CERN)

10/11/2025, 16:25

WG1 - Monolithic Sensors

The CASSIA (CMOS Active SenSor with Internal Amplification) project is focused on developing monolithic active pixel sensors (MAPS) with internal signal gain in the Tower 180nm CMOS process. The advantages of internal amplification include a higher input signal enabling simplification of in-pixel electronics, an improved signal-to-noise ratio for radiation hardness, and superior timing...

7. Limits of Spatial Resolution in TJ-65nm --- How Much Charge Information Do We Need?

Finn King (Deutsches Elektronen-Synchrotron (DE))

10/11/2025, 16:45

WG1 - Monolithic Sensors

The Analog Pixel Test Structures (APTS) are a family of sensor prototypes produced in the TPSCo CMOS 65 nm ISC technology. They contain 4x4 pixels of varying pitches between 10 and 25 μm, implement different diode designs, namely standard, n-blanket and n-gap, to tailor charge collection, and further design variations to optimize the sensor layout in the given process. The structures have been...

48. The OCTOPUS project: optimizing monolithic active pixel sensors for the next generation of lepton collider experiments

Roberto Russo (Austrian Academy of Sciences (AT))

10/11/2025, 17:05

WG1 - Monolithic Sensors

The OCTOPUS (Optimized CMOS Technology for Precision in Ultra-thin Silicon) project, part of the DRD3 collaboration, aims to develop Monolithic Active Pixel Sensors (MAPS) based on the TPSCo 65 nm CMOS process, designed to meet the key requirements of vertex detectors operating in the next generation of lepton colliders.
The sensor development is planned in two stages. The first large-area...

58. Status of the MANTA project

Michael Deveaux (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE))

10/11/2025, 17:25

WG1 - Monolithic Sensors

Developing such advanced MAPS technology may exceed the individual capacities of smaller experimental collaborations. The MANTA project addresses this challenge through a joint R&D initiative aimed at creating a versatile, configurable sensor platform. The sensor will be designed to adapt to various experimental environments via slow control mechanisms, enabling a wide range of use cases...

40. Porting the MALTA chip to the 65 nm TPSCo node: Conceptual Design Overview

Carlos Solans Sanchez (CERN), Thomas Koffas (Carleton University (CA))

10/11/2025, 17:45

WG1 - Monolithic Sensors

The existing MALTA design is employing low capacitance of the collection electrode together with full depletion of the sensitive volume and is fabricated in Tower 180 nm technology. Currently, further development of the MALTA chip is shifting towards substantially better timing performance (timing resolution <500 picoseconds) as well as improved integration capabilities of the sensor in larger...