Speaker
Description
Future high-energy physics experiments require tracking detectors with improved timing and spatial resolution, combined with a low material budget. The CASSIA (CMOS Active Sensor with Internal Amplification) project addresses these requirements by developing a monolithic pixel detector with internal amplification, achieved through the implementation of gain layers in an industrial 180 nm CMOS imaging process. The first prototype, CASSIA1, includes four 3 × 3 pixel matrices and 24 single-pixel structures with varying gain-layer geometries and electrode spacing, affecting gain, noise, and breakdown behavior.
CASSIA1 was characterized in a controlled environment using climate-chamber studies and both TCT and source measurements. The measurements confirm operation in both LGAD and SPAD regimes, soft-breakdown behavior allowing fine gain tuning, and low dark count rates suitable for high-SNR applications. The results obtained during this campaign were used to improve the design and make it compatible with in-pixel frontend electronics.
The next-generation CASSIA2 chip, also submitted in 180 nm, will feature larger matrices with a fully scaled frontend, combining mixed digital and analog readout. Its design will be presented, highlighting the challenges when integrating LGAD structures along CMOS circuitry. The different stages and design considerations, from in-pixel circuit placement to top-level digital readout architecture, will be discussed.